Memory Cell Stack Via Formation With Barrier Planarization

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Solution Overview

Problem

In memory device fabrication, undulating top surfaces of barrier materials can lead to unpredictable behavior and reduced performance in access lines, increasing complexity and resistance, which affects current delivery and overall device efficiency.

Innovation Solution

Planarizing the top surface of the barrier material before forming the metal layer for access lines, resulting in larger grain size and reduced undulations, thereby improving the predictability and uniformity of the metal layer's behavior and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the barrier material is formed without planarization, then the fabrication process is simpler and faster, but the access line behavior becomes unpredictable and resistance increases

Engineering Contradiction:
Improveaccess line behavior predictabilityVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The barrier material top surface is planarized before depositing the metal access line layer. This preliminary surface preparation ensures a flat substrate for metal deposition, which promotes uniform grain growth and predictable electrical behavior in the access lines, resolving the contradiction between manufacturing precision and process complexity by adding a controlled planarization step early in the fabrication sequence

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the barrier material top surface is undulating, then no additional processing steps are needed, but the metal layer grain size is reduced and resistance increases

Engineering Contradiction:
Improvecurrent delivery efficiencyVSAvoidfabrication process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Planarization of the barrier material top surface is performed as a preliminary step before metal layer deposition. This advance surface preparation creates optimal conditions for metal grain growth by providing a flat, uniform substrate, thereby ensuring larger grain sizes and lower resistance in the final access lines without complicating the overall fabrication approach

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If planarization is performed on the barrier material, then metal layer uniformity and grain size improve, but fabrication time and process steps increase

Engineering Contradiction:
Improvemetal layer uniformityVSAvoidfabrication cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The planarization step is integrated into the fabrication sequence as a preliminary preparation step before metal deposition. By performing surface planarization early in the process when the barrier material is freshly formed, the method achieves uniform metal layer characteristics and controlled grain growth without requiring additional time-consuming steps later in the fabrication cycle

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The planarization process modifies the physical state of the barrier material top surface by changing its surface topology from undulating to flat. This parameter change in surface morphology directly influences subsequent metal layer deposition, promoting uniform grain structure and reducing resistance while maintaining efficient fabrication timing through controlled process parameters

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances current delivery and reduces the complexity of memory device formation by decreasing resistance and improving the structural yield, leading to more efficient and reliable memory cell performance.

Implementation Method 1

planarizing a top surface of the barrier material

Methodology Applied
Scientific EffectChemical-Mechanical Planarization (CMP):

Data Source

PatentUS12022666B2Memory cell stack and via formation for a memory device
Publication Date: 2024.06.25 MICRON TECHNOLOGY INC
  • US12022666B2 patent drawing
  • US12022666B2 patent drawing
  • US12022666B2 patent drawing

AI summary

Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.