Memory Stack Voltage Swing Reduction for Cryogenic Data Links

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Solution Overview

Problem

Memory devices, such as DRAM arrays, face challenges in reducing power consumption and heat generation during data transport across links, which is critical in power-constrained environments like cryogenic computers where every unit of power requires significant heat removal to maintain low temperatures.

Innovation Solution

Implementing a reduced voltage swing for data transport across links within memory devices, using voltage reduction circuitry to lower the voltage before transmission and voltage amplification circuitry to restore it to the required level for processing, thereby reducing energy consumption and heat generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If standard voltage swing is used for data transport, then signal integrity and processing requirements are met, but power consumption and heat generation are high

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal integrity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the voltage parameter of data transport from standard voltage swing to reduced voltage swing. By lowering the voltage level during transport while using voltage amplification circuitry at destinations, the system achieves lower power consumption while maintaining signal integrity through proper signal restoration at intermediate points.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces voltage amplification circuitry as an intermediary component at the receiving ends of data links. These amplifiers act as mediators that restore the attenuated low-voltage signals to full strength, enabling reduced voltage transport without compromising signal integrity or processing requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If reduced voltage swing is used for data transport, then power consumption and heat generation are reduced, but signal strength for processing may be insufficient

Engineering Contradiction:
Improveheat generationVSAvoidsignal strength
Core Design Contradiction:
Object-generated harmful factorsVSStrength

Solution Approach 1:

The patent places voltage amplification circuitry at strategic intermediate points along data transport paths. These amplifiers serve as intermediaries that boost the weakened low-voltage signals back to processing-ready strength, allowing heat reduction during transport while maintaining adequate signal strength for subsequent processing operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system employs periodic voltage amplification at intermediate destinations along data links. Rather than maintaining constant high voltage throughout, the system uses periodic amplification bursts at key points to restore signal strength, enabling lower average power consumption while maintaining signal integrity where needed.

Inventive Principle:
Principle #19Periodic action

3Reliability

If voltage amplification circuitry is added to restore signal strength, then signal integrity is maintained, but device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies voltage amplification only locally at specific intermediate points where signals need restoration, rather than throughout the entire transport path. This localized approach to signal reinforcement maintains signal integrity where necessary while minimizing the overall complexity and power consumption of the amplification infrastructure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11257539B2Reduced transport energy in a memory system
Publication Date: 2022.02.22 RAMBUS INC
  • US11257539B2 patent drawing
  • US11257539B2 patent drawing
  • US11257539B2 patent drawing

AI summary

A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.