3D Memory Stack Separation Layout for Reliable Word Line Contacts
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Solution Overview
Problem
There is a need for a semiconductor device with improved reliability and integration to enhance data storage capacity in electronic systems.
Innovation Solution
A semiconductor memory device is designed with a peripheral circuit structure and a stacked structure that includes alternately stacked electrode layers and insulating layers, along with specific patterns and layers that enhance electrical connections and separation, leading to improved reliability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking multiple electrode layers (first electrode layers, second electrode layers) and insulating layers alternately in the vertical direction. This dimensional transition from planar to vertical stacking enables increased storage capacity while managing device complexity through structured layering and separation patterns.
2Device complexity
If stacked structure with alternating electrode and insulating layers is used, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the stacked structure into distinct segments including first electrode layers, second electrode layers, first inter-electrode insulating layers, and second insulating layers. Block separation patterns are introduced to further segment the structure into manageable blocks, reducing manufacturing precision requirements by creating modular units that can be fabricated and assembled systematically.
Solution Approach 2:
The patent introduces block separation patterns as intermediary structures between the stacked electrode and insulating layers. These separation patterns act as mediators that simplify the manufacturing process by providing reference structures for alignment and separation, thereby reducing the overall manufacturing precision requirements while maintaining integration.
3Reliability
If line separation pattern and block separation patterns are added, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces block separation patterns that extend into the stacked structure to divide it into distinct blocks, and line separation patterns that extend into the second insulating layer, second electrode layer, and first insulating layer to separate individual cells. This segmentation improves reliability by isolating potential failure points while maintaining overall device functionality through modular block organization.
Data Source
AI summary
A semiconductor memory device includes a peripheral circuit structure including peripheral circuits; a stacked structure on the peripheral circuit structure and including first electrode layers and first inter-electrode insulating layers that are alternately stacked; a first vertical pattern that extends into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a line separation pattern that extends into the second insulating layer, the second electrode layer, and the first insulating layer; and a second vertical pattern that extends into the second insulating layer, the second electrode layer, and the first insulating layer, where the second vertical pattern is electrically connected to the first vertical pattern.