3D Memory Stack Layout for Stable High Word-Line Integration
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Solution Overview
Problem
The stability of manufacturing processes and structural stability is compromised as the number of stacked word lines increases in three-dimensional semiconductor memory devices, affecting the integration and performance of the device.
Innovation Solution
The semiconductor memory device is designed with a first stack and a second stack, featuring lower and upper conductive patterns with stepped structures, supported by insulating pillars, and a channel structure surrounded by a memory layer, which are formed through a method involving sacrificial pillars and insulating layer formation to enhance structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to increase the degree of integration, then the integration is improved, but the stability of manufacturing processes and structural stability deteriorates
Solution Approach 1:
The gate electrode stack is segmented into multiple stacks (first stack, second stack, third stack) positioned at different locations. Each stack contains a reduced number of word lines (e.g., 3-5 word lines per stack), which divides the total integration capacity across multiple smaller units. This segmentation reduces the complexity and manufacturing difficulty of each individual stack while achieving high overall integration through the combination of multiple stacks.
Solution Approach 2:
The patent transitions from a single vertical stack to a three-dimensional arrangement of multiple stacks positioned at different lateral locations (first, second, and third stacks). This spatial distribution across multiple dimensions allows the device to achieve higher overall integration by utilizing both vertical stacking and lateral arrangement, effectively converting a one-dimensional stacking problem into a multi-dimensional solution.
2Quantity of substance
If the number of stacked word lines is increased, then the degree of integration is improved, but the structural stability deteriorates
Solution Approach 1:
The gate electrode stack is segmented into multiple stacks (first stack, second stack, third stack) positioned at different locations. Each stack contains a reduced number of word lines (e.g., 3-5 word lines per stack), which divides the total integration capacity across multiple smaller units. This segmentation reduces the complexity and manufacturing difficulty of each individual stack while achieving high overall integration through the combination of multiple stacks.
Solution Approach 2:
The patent transitions from a single vertical stack to a three-dimensional arrangement of multiple stacks positioned at different lateral locations (first, second, and third stacks). This spatial distribution across multiple dimensions allows the device to achieve higher overall integration by utilizing both vertical stacking and lateral arrangement, effectively converting a one-dimensional stacking problem into a multi-dimensional solution.
Data Source
AI summary
A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.