3D Memory Stacked Body Alignment via Wet Etching

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Solution Overview

Problem

The formation of three-dimensional semiconductor memory devices with increased electrode films leads to a high aspect ratio of memory holes, making the alignment between stacked bodies challenging and costly, resulting in potential displacement issues during the manufacturing process.

Innovation Solution

The use of alignment marks and steps in the scribing region to align the lower and upper stacked bodies, allowing for precise formation of memory holes and reducing the need for costly dry etching processes by utilizing wet etching for the insulating film, thereby improving the yield and reducing manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of electrode films stacked is increased to increase the number of memory cells, then the storage capacity is improved, but the aspect ratio of memory holes rises making alignment more difficult and costly

Engineering Contradiction:
Improvenumber of memory cellsVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming alignment marks and steps in the scribing region before forming the memory holes. These alignment features are prepared in advance to guide the precise formation of memory holes through the stacked bodies, ensuring accurate alignment between lower and upper stacked bodies even as the number of electrode films increases.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses alignment marks and overlay marks as intermediary elements to facilitate the alignment process. These marks serve as mediators between the lower and upper stacked bodies, enabling precise positioning without directly involving the memory hole formation process itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If alignment marks and overlay marks are formed to improve alignment precision, then manufacturing precision is improved, but the process cost increases

Engineering Contradiction:
Improvealignment precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges the alignment mark formation with the existing scribing region structure. By integrating alignment marks into the scribing region that is already being processed, the patent avoids adding separate alignment mark formation steps, thereby maintaining manufacturing precision while controlling process costs.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The scribing region serves multiple functions: it provides structural definition for the semiconductor device and simultaneously serves as the location for alignment marks. This multi-functionality reduces the need for additional dedicated alignment structures and processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If dry etching is used to form memory holes through stacked bodies with high aspect ratio, then manufacturing precision is improved, but the process complexity and cost increase

Engineering Contradiction:
Improvememory hole formation precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the etching parameter from dry etching to wet etching for forming memory holes. This parameter change simplifies the process while maintaining adequate precision by utilizing the alignment marks and steps previously formed in the scribing region to guide the wet etching process through the stacked bodies.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses displacement between the lower and upper stacked bodies, enhances productivity, and lowers manufacturing costs by using wet etching for the insulating film, thus improving the overall efficiency of semiconductor memory device production.

Implementation Method 1

there are formed an alignment mark and an overlay mark to perform the alignment between the lower stacked body and the upper stacked body

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10115680B2Semiconductor memory device and method for manufacturing the same
Publication Date: 2018.10.30 KIOXIA CORP
  • US10115680B2 patent drawing
  • US10115680B2 patent drawing
  • US10115680B2 patent drawing

AI summary

According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate. The second insulating film is provided in a second region on the substrate, and has a first thickness in a stacking direction of the first stacked body. The second stacked body is provided on the second insulating film. The second stacked body includes a first film and a third insulating film stacked alternately on one another. The uppermost first film in the first films of the second stacked body is located at a first distance in the stacking direction from the upper surface of the substrate. The first thickness is a thickness not less than 30 percent of the first distance.