3D Memory Device Stacked Conductive Layers Integration
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Solution Overview
Problem
Current memory devices face challenges in increasing their degree of integration, which is essential for enhancing storage capacity and performance, particularly in three-dimensional (3D) memory devices.
Innovation Solution
The proposed memory device includes a stacked structure with alternating first and second conductive layers and channel structures that penetrate these layers, forming an interface between them, allowing for increased integration by simplifying the manufacturing process and improving stability through the use of insulating layers and separation patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional manufacturing processes are used for 3D memory devices, then manufacturing complexity increases, but degree of integration improvement is limited
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming alternating first and second material layers, creating first holes through the stacked body, forming mask patterns to open specific groups of holes, etching second holes through first material layers, forming first conductive layers in second holes, and finally forming channel structures. This segmentation allows each step to be optimized independently, reducing overall manufacturing complexity while enabling higher degree of integration through systematic progression.
Solution Approach 2:
The patent transitions from planar 2D memory structures to three-dimensional stacked structures with alternating material layers extending in multiple directions. Channel structures penetrate through the stacked body in the third direction, while first conductive layers are formed in holes extending in different directions, creating a multi-dimensional architecture that significantly increases storage density and degree of integration without proportionally increasing manufacturing complexity.
2Quantity of substance
If stacked structure with alternating conductive layers is implemented, then degree of integration increases, but manufacturing precision requirements increase
Solution Approach 1:
Mask patterns serve as intermediary elements that selectively open first groups of holes in the separation area while blocking second groups of holes in the first and second areas. This intermediary step allows precise control over where etching occurs, enabling the formation of first conductive layers in specific locations with high precision. The mask pattern acts as a template that guides subsequent etching processes, ensuring accurate positioning of conductive layers and channel structures.
Solution Approach 2:
The patent applies different properties to different regions: first material layers and second material layers have different etch selectivities, allowing selective removal of first material layers through etching processes. The mask pattern opens holes in specific locations (separation area) while blocking others (first and second areas). This local differentiation enables precise control over the manufacturing process, achieving high manufacturing precision in forming conductive layers and channel structures at specific positions within the stacked body.
Data Source
AI summary
Provided herein is a memory device and a method of manufacturing the memory device. The memory device includes a first conductive layer extending in a first direction, a second conductive layer extending from the first conductive layer in a second direction intersecting the first direction, a plurality of first channel structures penetrating the first conductive layer and disposed to be spaced apart from each other in the first direction, and a plurality of second channel structures penetrating the second conductive layer, wherein the first conductive layer may form an interface with the second conductive layer, and the interface may be disposed between the plurality of first channel structures and the plurality of second channel structures.