Non-Volatile Memory Stacked Structure Parasitic Capacitance
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Solution Overview
Problem
Current non-volatile memory devices with anti-fuse gate transistors require additional external circuits for voltage reduction, leading to increased device size and reduced integration due to the need for high-voltage resistance, and are prone to miswriting and leakage issues.
Innovation Solution
A non-volatile memory device structure that stacks materials with different dielectric coefficients to enhance parasitic capacitance, allowing the device to withstand high voltages without external voltage reduction circuits and includes a design that can turn off the device in case of miswriting or high leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a transistor is connected in series with an anti-fuse transistor to form a two-transistor structure for high-voltage writing, then the device can withstand high voltage during programming, but the device area is enlarged and integration is reduced
Solution Approach 1:
The patent embeds the stacked structure (comprising the anti-fuse transistor and select transistor) within a shared substrate area, nesting multiple functional components in a compact arrangement. The select transistor is integrated alongside the anti-fuse transistor, with shared source/drain regions, effectively nesting the voltage protection function within the existing memory cell footprint rather than adding external circuits.
Solution Approach 2:
The patent transitions from a planar two-transistor series connection to a three-dimensional stacked configuration. The select transistor is positioned above or below the anti-fuse transistor layer, utilizing the vertical dimension to accommodate the additional transistor functionality without increasing the lateral device area. This dimensional change allows high-voltage withstanding capability to be achieved within the same footprint.
2Strength
If the gate dielectric layer thickness is increased to prevent transistor collapse under high voltage, then the transistor can withstand high voltage, but the device area is enlarged
Solution Approach 1:
The patent applies different gate dielectric layer thicknesses to different regions: the anti-fuse transistor has a thicker gate dielectric layer (first thickness) to withstand high voltage, while the normal transistor has a thinner gate dielectric layer (second thickness) for standard operation. This localized differentiation allows each transistor to be optimized for its specific voltage requirements without unnecessarily increasing the overall device area.
Solution Approach 2:
The patent changes the gate dielectric layer thickness parameter selectively for different transistors within the same device. By adjusting this critical parameter locally rather than uniformly across the entire device, the solution achieves high-voltage withstanding capability where needed while maintaining compact dimensions overall.
3Reliability
If an external circuit is added for voltage reduction, then the transistor is protected from collapse, but the device complexity increases
Solution Approach 1:
The patent merges the voltage protection function into the intrinsic structure of the memory device itself by using the stacked transistor configuration and selective gate dielectric thickness. The select transistor and anti-fuse transistor are combined in a single integrated structure where the select transistor naturally limits the voltage applied to the anti-fuse transistor, eliminating the need for separate external voltage reduction circuits.
Solution Approach 2:
The device structure itself provides the voltage protection function through its internal configuration. The stacked transistor arrangement with appropriate dielectric thicknesses enables the device to self-regulate and protect against voltage-induced collapse without requiring external assistance or additional protection circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables higher device integration and improved performance by eliminating the need for external voltage reduction circuits and ensuring normal operation even with defects, while maintaining compatibility with standard logic low-voltage manufacturing processes.
Implementation Method 1
stacks materials with different dielectric coefficients to enhance parasitic capacitance, allowing the device to withstand high voltages
Implementation Method 2
a high voltage may be applied to the anti-fuse transistor to cause a gate dielectric layer therein to collapse, so that the anti-fuse is in an 'On' state
Data Source
AI summary
A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.