3D Memory Stacked Structures for High Density
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Solution Overview
Problem
Existing photolithography technology restricts the size reduction of two-dimensional memory cell arrays and three-dimensional memory cell arrays, limiting memory density due to limitations in reducing the distance between memory cells and complexity in manufacturing processes.
Innovation Solution
A manufacturing method involving stacked structures with alternating insulation layers of different etching rates, where trenches are formed using isotropic etching and filled with conductive layers, allowing for reduced bit line size and distance between memory cells, enabling higher memory density by lifting photolithography technology restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photolithography technology is used to reduce the size of memory cell arrays, then the distance between adjacent memory cells can be reduced, but the memory density decreases due to process limitations
Solution Approach 1:
The patent transitions from a two-dimensional memory cell array to a three-dimensional stacked structure with alternating conductive and insulation layers extending in the vertical direction. This dimensional change allows memory cells to be arranged in multiple layers, increasing storage capacity without reducing the lateral distance between cells, thus overcoming photolithography limitations.
Solution Approach 2:
The patent employs composite material structures with alternating conductive layers (containing charge storage structures) and insulation layers. This composite approach enables vertical stacking while maintaining electrical isolation between layers, achieving high density through three-dimensional arrangement rather than lateral compression.
2Quantity of substance
If the size of memory cells is reduced to improve data storage capacity, then more cells can be packed, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the memory structure into multiple thin alternating layers of conductive and insulation materials stacked vertically. Each layer is formed through separate deposition and etching processes, but the modular layered architecture simplifies the overall manufacturing compared to attempting to miniaturize entire memory cells in two dimensions.
Solution Approach 2:
By moving to three-dimensional vertical stacking, the patent increases data storage capacity without requiring proportional reduction in cell size. The vertical dimension provides additional space for charge storage structures, enabling higher capacity while maintaining manageable lateral dimensions and process complexity.
3Quantity of substance
If three-dimensional memory cell arrays are formed to increase storage capacity, then memory density improves, but the manufacturing process becomes rather complicated
Solution Approach 1:
The patent utilizes parameter changes in the form of alternating material layers with different etching rates. The first insulation layers have lower etching rates while second insulation layers have higher etching rates, enabling selective removal of specific layers to form trenches. This parameter variation simplifies the formation of three-dimensional structures compared to conventional approaches.
Solution Approach 2:
The patent introduces mask layers as intermediaries to control the etching process. These mask layers selectively protect certain regions during etching, enabling precise formation of trenches and charge storage structures without requiring complex direct patterning of the three-dimensional structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a memory with relatively high memory density by reducing the distance between adjacent memory cells and overcoming the limitations of existing photolithography technology, enabling more efficient data storage capacity.
Implementation Method 1
The trenches are formed by performing an isotropic etching process to remove a portion of each of the second insulation layers
Implementation Method 2
An anisotropic etching process is performed to remove the conductive material layer outside the trenches
Data Source
AI summary
A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.