Memory Programming With Staged Current Levels

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Solution Overview

Problem

Modern memory arrays require high current and long durations for programming, leading to inefficient performance in terms of power consumption and speed.

Innovation Solution

A method involving multiple current levels and adjusted durations is employed to program memory elements, optimizing the balance between programming time and power consumption by adjusting current levels in stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high current and long duration are used for programming memory elements, then programming reliability is improved, but power consumption increases and programming speed decreases

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The programming current is divided into multiple discrete levels (first current level, second current level, third current level) applied in sequential time periods. This segmentation allows the memory element to be programmed through staged current application, where higher current levels are used for critical programming phases and lower current levels for subsequent phases, thereby reducing overall power consumption while maintaining programming reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The current level is dynamically adjusted during the programming process rather than maintaining a constant high current. The method transitions from a first current level to a second current level, and then to a third current level across different time periods. This dynamic adjustment optimizes the balance between programming effectiveness and power consumption by applying higher currents only when necessary and reducing currents during less critical programming phases.

Inventive Principle:
Principle #15Dynamics

2Reliability

If high current and long duration are used for programming memory elements, then programming reliability is improved, but programming speed decreases

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidprogramming speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The programming process is segmented into multiple time periods with distinct current levels. By dividing the programming operation into staged phases with different current intensities, the method achieves reliable programming without requiring uniformly high current throughout the entire duration, thus improving programming speed while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The programming current is applied periodically with varying levels across different time periods rather than as a continuous constant current. This periodic action with modulated current levels enables efficient programming by concentrating higher current application during critical phases while using lower currents during other phases, thereby reducing total programming time while ensuring reliable programming.

Inventive Principle:
Principle #19Periodic action

3Productivity

If multiple current levels and adjusted durations are used for programming, then power consumption is optimized and programming time is reduced, but device complexity increases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidcontrol circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control circuit generates multiple discrete current levels through segmented operation across different time periods. This segmentation approach, while adding control complexity, enables precise optimization of power consumption and programming time by applying appropriate current levels at appropriate times, thereby achieving high programming efficiency that justifies the increased control complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12417806B2Method for programming memory
Publication Date: 2025.09.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12417806B2 patent drawing
  • US12417806B2 patent drawing
  • US12417806B2 patent drawing

AI summary

A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.