Memory Device Staged Data Transfer for Reduced Latency
Solution Overview
Problem
Existing memory devices face delays in data reading due to the need to wait for both the Most Significant Bit (MSB) and Least Significant Bit (LSB) data states to be determined before transferring data, which limits the speed of data access.
Innovation Solution
Implementing a method where the MSB data state is determined and transferred during a first sense phase, followed by the LSB data state during a second sense phase, allowing for partial data transfer before the LSB is fully determined, thus reducing the overall delay in data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory device waits for both MSB and LSB data states to be determined before transferring data, then data accuracy is ensured, but data access speed deteriorates
Solution Approach 1:
The patent applies preliminary action by determining and transferring the MSB data state during the first sense phase before the LSB data state is fully determined. The control circuitry initiates data transfer operations in advance during the first sense phase, performing partial data transfer while the second sense phase is still in progress. This allows the memory device to begin transferring data before both data states are completely determined, thereby improving data access speed while maintaining data accuracy through the staged approach.
2Reliability
If the memory device transfers data only after both MSB and LSB are determined, then data integrity is maintained, but data latency increases
Solution Approach 1:
The patent applies segmentation by dividing the data transfer process into two distinct phases corresponding to the two sense phases. During the first sense phase, the MSB data state is determined and transferred. During the second sense phase, the LSB data state is determined and transferred. This segmentation allows partial data transfer to occur during the first sense phase rather than waiting for complete determination of both data states, thereby reducing data latency while maintaining data integrity through structured phased transfer.
Solution Approach 2:
The control circuitry performs preliminary data transfer actions during the first sense phase by initiating the transfer of MSB data before the second sense phase completes. This preliminary action reduces the overall data latency by overlapping the data transfer operation with the ongoing sensing operations, while data integrity is preserved through the systematic phased approach to determining and transferring data states.
3Measurement precision
If the memory device completes the full sense operation before data transfer, then measurement completeness is ensured, but response time deteriorates
Solution Approach 1:
The patent applies preliminary action by initiating data transfer during the first sense phase before the complete sense operation finishes. The control circuitry determines the MSB data state during the first sense phase and initiates transfer of this data while the second sense phase is still in progress. This preliminary transfer action reduces response time by overlapping operations, while measurement completeness is maintained because the full sense operation still completes and determines both MSB and LSB data states.
Solution Approach 2:
The patent applies continuity of useful action by overlapping the data transfer operation with the sensing operations. The transfer of MSB data begins during the first sense phase and continues while the second sense phase determines the LSB data state. This continuous overlapping of useful actions (sensing and transferring) maximizes resource utilization and reduces idle time, thereby improving response time while ensuring complete measurement through the completion of both sense phases.
Data Source
AI summary
Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.