Memory System Peak Current Control via Staggered Clock Synchronization
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Solution Overview
Problem
Semiconductor memory systems face challenges in managing peak currents, which can lead to malfunctions and operational deterioration due to overlapping peak currents, requiring a balance between reliability and performance.
Innovation Solution
A memory system with a controller and multiple memory devices, where each device generates an internal clock in synchronization with a processor clock, allowing peak current generation operations to occur at different times to prevent overlapping, thereby controlling peak currents without impairing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control operations are performed to prevent overlapping of peak currents, then reliability is improved, but operational delays occur
Solution Approach 1:
The patent implements periodic action by dividing peak current generation operations into different time slots using synchronized internal clocks. Each memory device generates peak currents at different periodic intervals determined by clock phases, ensuring that peak currents from multiple devices do not overlap in time. This periodic scheduling allows multiple devices to operate simultaneously without interference, improving reliability while maintaining high operational throughput without delays.
2Productivity
If multiple memory devices operate simultaneously, then productivity is improved, but peak currents overlap causing malfunctions
Solution Approach 1:
The patent applies segmentation by dividing the simultaneous operation of multiple memory devices into segmented time slots through clock synchronization. Each memory device is assigned a specific time slot for peak current generation based on its internal clock phase. This segmentation allows multiple devices to operate in parallel during their respective time slots, maintaining high productivity while preventing harmful current overlaps that would cause malfunctions.
Data Source
AI summary
A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.