3D Memory Stair Structure for Contact Height Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently controlling the height of stair portions in contact regions, leading to increased chip area and complexity in manufacturing processes.
Innovation Solution
The semiconductor device incorporates a design where the height of stair portions in contact regions is controlled by forming stacked bodies with alternating conductive and insulating layers, allowing for reduced chip area and simplified process steps by ensuring the lower and upper stacked bodies have the same height without relying on substrate level differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If substrate level differences are used to control stair portion heights, then contact region heights can be controlled, but chip area increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from controlling stair portion heights through substrate level differences (horizontal dimension) to controlling them through the thickness of conductive and insulating layers (vertical dimension). This allows height control without increasing chip area, as the stacking is done vertically within the same footprint.
Solution Approach 2:
The patent divides the contact region structure into multiple segments: alternating conductive layers and insulating layers stacked vertically. Each layer can be independently formed and controlled, allowing precise control of the overall stair portion height without requiring substrate level adjustments.
2Manufacturing precision
If substrate level differences are used to control stair portion heights, then contact region heights can be controlled, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into independent layer formation steps. Each conductive layer and insulating layer is formed separately using standard deposition and patterning techniques, avoiding the need for complex substrate level adjustment processes.
Solution Approach 2:
The patent moves the height control mechanism from the substrate level (requiring complex leveling processes) to the layer thickness dimension (controlled by standard thin film deposition processes), thereby simplifying the manufacturing workflow.
3Area of stationary object
If alternating conductive and insulating layers are stacked to control stair portions, then chip area is reduced, but the structure becomes more complex
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple conductive and insulating layers, thereby achieving high integration and reduced chip area without significantly increasing lateral structural complexity.
Solution Approach 2:
The alternating conductive and insulating layers serve multiple functions: they define the stair portion heights, provide electrical connections, and act as barriers. This multi-functionality reduces the need for additional separate structures, keeping the overall design relatively simple despite the stacked configuration.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.