3D Memory Stair-Step Insulation for Dense Vertical Cell Arrays
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Solution Overview
Problem
Current methods for forming integrated circuitry, particularly memory arrays, face challenges in efficiently creating three-dimensional structures with vertically-stacked memory cells and stair-step structures that require precise electrical coupling and insulation, which can be complex and costly.
Innovation Solution
A method involving a 'gate-last' process where a stack of alternating insulative and conductive tiers is formed, with channel openings etched to directly couple channel material to the conductor tier, and a stair-step structure is created using a first liquid with insulative physical objects that are removed to leave voids, filled with a second liquid that solidifies into insulative material, facilitating the formation of memory cells and peripheral circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to form three-dimensional memory structures with vertically-stacked cells and stair-step structures, then memory capacity and integration density are improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by forming the stair-step structure and insulative material layers before creating the channel openings and memory cells. The insulative material is deposited and patterned in advance to define the stair-step regions, which then guide subsequent processing steps. This preliminary structuring simplifies the formation of vertically-stacked memory cells by pre-establishing the electrical isolation pathways and conductor tier connections, reducing the complexity of later manufacturing steps while maintaining high integration density
Solution Approach 2:
The patent segments the memory array into multiple vertically-stacked tiers with alternating insulative and conductive layers. Each tier can be independently addressed and controlled through the stair-step structure, allowing parallel processing and fabrication. The segmentation of the three-dimensional space into discrete memory blocks and wordline tiers enables modular manufacturing approaches, reducing overall process complexity while increasing productivity through parallel fabrication of multiple memory tiers
2Reliability
If precise electrical coupling and insulation are implemented in vertically-stacked memory cells, then device performance and reliability are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses an intermediary approach by introducing a stair-step structure composed of insulative material that acts as a mediator between vertically-stacked memory cells. This stair-step structure provides predefined electrical isolation and coupling pathways, ensuring reliable electrical connections without requiring ultra-precise direct alignment between stacked components. The insulative material in the stair-step regions serves as an intermediary that guarantees electrical isolation while the conductor tiers provide reliable coupling, reducing the stringency of alignment precision requirements
Solution Approach 2:
The patent employs parameter changes by varying the physical and electrical properties of materials at different vertical levels. The insulative material properties (dielectric constant, thickness) are specifically tailored for the stair-step regions to optimize electrical isolation, while conductor tier materials are selected for optimal electrical coupling. This parameter optimization at different levels ensures reliable electrical performance while accommodating realistic manufacturing precision capabilities
3Quantity of substance
If vertically-stacked memory cells with stair-step structures are formed, then memory capacity increases, but process time and manufacturing steps increase
Solution Approach 1:
The patent merges multiple functions into the stair-step structure, which simultaneously provides electrical isolation, mechanical support, and process alignment references for vertically-stacked memory cells. The insulative material deposition and patterning steps are combined with the formation of wordline connections and bitline structures, reducing the total number of discrete manufacturing steps. This functional merging increases memory capacity through vertical stacking while minimizing the increase in manufacturing cycle time
Data Source
AI summary
A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed.