3D Memory Stair-Step Lining for Direct Via Coupling and Isolation
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Solution Overview
Problem
Current memory circuitry technologies face challenges in efficiently forming memory arrays with vertically-stacked memory cells, particularly in achieving direct electrical coupling and anchoring effects without alternative processing, while maintaining structural integrity and electrical isolation between memory blocks.
Innovation Solution
The method involves forming a stack with vertically-alternating insulative and conductive tiers, including a stair-step region with a lining of specific resistance materials and insulative material, and conductive vias that extend through the insulative material and lining to provide direct electrical access and isolation, facilitating the formation of memory cells with charge-blocking and storage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory array formation methods are used, then manufacturing processes are simpler, but direct electrical coupling and anchoring effects cannot be achieved
Solution Approach 1:
The conductor tiers are formed and extended into the stair-step region before the memory cells are fully constructed. This preliminary extension creates pre-formed contact regions that enable direct electrical coupling with the channel material of vertically-stacked memory cells, eliminating the need for subsequent complex alignment and connection processes
Solution Approach 2:
The memory array is divided into multiple memory blocks with intermediate regions between them. The conductor tiers are segmented to extend into these intermediate regions, creating discrete contact regions for each memory block. This segmentation enables direct electrical coupling within each block while maintaining isolation between blocks
2Productivity
If vertically-stacked memory cells are formed, then memory density is improved, but structural integrity and anchoring effects are compromised
Solution Approach 1:
The conductor tiers are extended into the stair-step region and prepared as anchoring structures before the vertically-stacked memory cells are constructed. This preliminary preparation ensures that when the memory cells are formed, their channel material can directly couple with the pre-positioned conductor tiers, providing both electrical connection and structural support
Solution Approach 2:
The conductor tiers are nested within and extended into the intermediate regions between memory blocks. This nested configuration allows the conductor tiers to serve dual purposes: providing electrical connectivity within memory blocks and acting as structural anchors that enhance the overall integrity of the vertically-stacked memory cell structure
Data Source
AI summary
Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. A lining has a specific resistance of at least 1×104 ohm·m at 20° C. atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. The lining comprises at least one of (a), (b), (c), and (d), where: (a): M1xM2yOz having a specific resistance of at least 1×104 ohm·m at 20° C. and where M1 and M2 are each a different one of Hf, Zr, Al, Ta, Sc, and Y; “z” is greater than zero; and at least one of “x” and “y” is greater than zero; (b) BtCwOv having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “t” and “v” is greater than zero (c): BrCs having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “r” and “s” is greater than zero; and (d): BkChNp having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “k” and “p” is greater than zero. Insulative material in the cavity is directly above the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Conductive vias extend through the insulative material and the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Methods are disclosed.