Memory Stair-Step Via Structure With Thickened Cavity Lining
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Solution Overview
Problem
The formation of through-array vias (TAVs) in memory circuitry is hindered by tapered sidewalls of cavities, leading to etch stopping issues and potential shorting due to the etch-stopping function of silicon-nitride lining, which can cause via openings to bend and result in failed circuitry.
Innovation Solution
A method involving the formation of a stack with vertically-alternating conductive and insulative tiers, where an insulating lining is thicker at the bottom part of cavities and insulative material is formed above, allowing conductive vias to extend through, alleviating etch-stopping issues and preventing shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon-nitride lining is used to provide etch-stopping function in cavity cavities, then etching control is improved, but via openings may bend and cause shorting between conductive tiers
Solution Approach 1:
The cavity structure is segmented into multiple regions with different lining thicknesses: a first portion with thicker silicon-nitride lining providing etch-stop function, and a second portion with thinner lining allowing proper via formation. This segmentation resolves the contradiction by spatially separating the etch-stopping function from the via-opening region, preventing via bending while maintaining etching control where needed.
Solution Approach 2:
The silicon-nitride lining is applied with non-uniform thickness distribution: thicker in the first portion of the cavity for etch-stopping, and thinner in the second portion for via formation. This local quality variation allows the same material to serve different functions in different locations, resolving the contradiction between etching control and preventing via shorting.
2Ease of manufacture
If tapered sidewalls of cavities are present, then cavity formation is simplified, but etch stopping issues occur leading to via opening bending
Solution Approach 1:
The cavity sidewalls are segmented into different regions: an upper portion with tapered geometry for ease of formation, and a lower portion with vertical sidewalls and thicker lining for precise via opening control. This segmentation allows the cavity to benefit from simplified formation processes while maintaining precision in the via-opening region.
Solution Approach 2:
The cavity structure is preliminarily formed with tapered sidewalls for ease of manufacture, then subsequently modified in the via-opening region by adjusting lining thickness and sidewall geometry to vertical profiles. This preliminary action followed by targeted modification resolves the contradiction by first achieving easy formation, then correcting the precision issues in specific regions.
Data Source
AI summary
A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. The first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. An insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. Individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. The insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. Insulative material is formed in the cavity directly above the insulating lining. Conductive vias are formed through the insulative material and the insulating lining. Individual of the conductive vias are directly above and directly against the conducting material of the tread of individual of the stairs. Other embodiments, including structure, are disclosed.