Memory Stair Structure With Wet Etching for Lower-Cost Interconnects
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing manufacturing costs and maintaining structural integrity during the formation of terrace portions and interconnects, leading to potential yield issues and increased costs due to complex etching and filling processes.
Innovation Solution
The semiconductor memory device employs a manufacturing method that forms stair structures without removing insulators above terrace portions, using wet etching to remove sacrificial members and filling insulating layers, which reduces the amount of material to be etched and filled, thereby lowering costs and minimizing the risk of structural discrepancies between cell and hookup areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate manufacturing processes are used for cell area and hookup area, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the manufacturing processes for the cell area and hookup area into a single integrated process. The ladder portion structure allows simultaneous etching and insulator filling across both regions using the same process parameters, eliminating the need for separate manufacturing sequences and reducing overall process complexity while maintaining precision.
Solution Approach 2:
The hookup area is segmented into ladder portions with terrace portions that are formed simultaneously with the cell area structures. This segmentation allows the hookup area to be processed in parallel with the cell area, enabling concurrent etching and filling operations without compromising the precision required for either region.
2Manufacturing precision
If multiple sequential steps are used for insulator filling, then manufacturing precision is maintained, but productivity decreases
Solution Approach 1:
The patent implements continuous insulator filling where the insulator is deposited in a single continuous process that spans both the cell area and hookup area simultaneously. The ladder portion structure enables the filling process to proceed without interruption across multiple regions, eliminating sequential filling steps and improving throughput while maintaining uniform insulation quality.
Solution Approach 2:
The ladder portion structure is pre-formed with terrace portions that are ready to receive insulator material in the same process step as the cell area structures. This preliminary preparation allows the insulator filling to occur in a single continuous action without requiring separate preparation steps, thereby increasing productivity.
3Manufacturing precision
If dry etching is used, then manufacturing precision is improved, but loss of substance increases due to sacrificial material removal
Solution Approach 1:
The patent changes the etching parameter from dry etching to wet etching for the ladder portion structures. This parameter change allows for more controlled material removal with wet etching, reducing the loss of sacrificial material while maintaining the precision required for forming the ladder portions and terrace structures.
4Ease of manufacture
If insulators are removed above terrace portions, then ease of manufacture is improved, but loss of substance increases
Solution Approach 1:
The ladder portion structure is designed with terrace portions that are formed in advance during the etching process, creating a ready-made structure for subsequent insulator filling. This preliminary formation eliminates the need to remove insulators above terrace portions, as the structure is already in place to receive the insulator material directly.
Solution Approach 2:
Instead of viewing the insulator material above terrace portions as waste to be removed, the patent converts this into a beneficial feature by designing the ladder structure to retain and utilize this insulator material as part of the final insulated structure, thereby eliminating the harmful effect of material loss while simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and improves yield by minimizing the number of manufacturing steps and preventing structural failures due to reduced etching and filling requirements, while maintaining the integrity of the memory device's structure.
Implementation Method 1
uses wet etching to reduce the amount of sacrificial material and insulator needed
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.