3D Memory Staircase Asymmetry for Chip Area Reduction
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Solution Overview
Problem
Current three-dimensional NAND memory devices have a significant portion of their chip area dedicated to word line decoder circuitry and sense amplifier circuitry, which increases manufacturing costs and complexity, and existing methods form unnecessary staircase regions on both sides of the memory array, wasting valuable space.
Innovation Solution
The method involves forming a three-dimensional semiconductor structure with a first and second tier structure, where only staircase regions are formed on the sides facing the word line decoder circuitry, eliminating the need for dummy staircase regions on the sense amplifier circuitry side, thereby optimizing chip space and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If staircase regions are formed on both sides of the memory array, then word line decoder circuitry can be accommodated, but valuable chip space is wasted on unnecessary dummy staircase regions
Solution Approach 1:
The patent applies asymmetry by forming staircase regions only on the sides of the memory array that face the word line decoder circuitry, while omitting staircase regions on sides facing sense amplifier circuitry. This asymmetric configuration eliminates unnecessary dummy staircase regions, thereby reducing wasted chip space and simplifying the manufacturing process by removing redundant etching steps.
Solution Approach 2:
The patent extracts and removes the unnecessary staircase regions from the device structure. By identifying that staircase regions are only needed adjacent to word line decoder circuitry, the invention selectively eliminates staircase regions from other areas of the chip, thereby reducing overall device complexity and chip area without compromising functionality.
2Area of stationary object
If peripheral devices are placed under the memory array, then chip space is optimized, but access to peripheral devices becomes more complex
Solution Approach 1:
The patent utilizes the vertical dimension by allowing peripheral devices to be positioned underneath the memory array structure. This three-dimensional stacking approach enables efficient space utilization on the chip while maintaining separate functional regions, as peripheral devices access signals through vertical interconnects rather than lateral routing.
Data Source
AI summary
Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.