3D Memory Staircase Landing Pads for Uniform BEOL Exposure
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, scaling becomes challenging and costly, and 3D memory architecture is needed to address density limitations, but it introduces manufacturing complexity and yield variations due to differential BEOL exposure times across staircase structures.
Innovation Solution
A staircase structure for 3D memory devices is formed using a series of layer stacks with insulating and conductive materials, where each layer stack includes a first insulating material layer and a second conductive material layer, with landing pads and spacers to facilitate even BEOL processing, reducing process variation and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D memory architecture is used to address density limitations, then memory density is improved, but manufacturing complexity and yield variations increase due to differential BEOL exposure times
Solution Approach 1:
The patent applies equipotentiality by designing the staircase structure with uniform landing pad heights across all tiers. This ensures that during back-end-of-line (BEOL) processing, all tiers are exposed to the same process conditions and durations, eliminating differential exposure times. The landing pads are configured at a common height reference plane, creating an equipotential surface that equalizes the manufacturing environment across the 3D structure, thereby reducing yield variations while maintaining high memory density.
2Quantity of substance
If 3D memory architecture is used to address density limitations, then memory density is improved, but yield variations increase due to differential BEOL exposure times
Solution Approach 1:
The staircase structure implements equipotentiality by establishing a common reference plane for all landing pads across different tiers. This design ensures that during BEOL processing steps such as deposition and etching, all tiers experience identical process conditions and exposure times. The uniform height configuration eliminates the yield variations that would otherwise arise from differential exposure, thereby improving reliability and consistency of manufacturing outcomes while achieving high memory density.
Solution Approach 2:
The patent employs parameter changes by carefully controlling the height parameters of the landing pads and inter-tier dielectric layers. The landing pads are designed with specific thickness parameters (e.g., 50-200 nm) and the inter-tier dielectric layers are configured with precise thickness control. These parameter adjustments ensure that the top surfaces of landing pads across all tiers align at a common height, transforming the variable exposure conditions into uniform parameters throughout the BEOL processing sequence.
3Quantity of substance
If staircase structure with multiple tiers is formed, then memory density is improved, but process variation increases due to differential exposure times
Solution Approach 1:
The staircase structure resolves process variation by creating an equipotential configuration where all landing pads across multiple tiers are positioned at the same height relative to a common reference plane. This design ensures that during BEOL processing, deposition layers and etch patterns are applied uniformly across all tiers simultaneously. The equipotential arrangement eliminates the process variation that would result from differential exposure times, enabling precise manufacturing control while achieving high memory density through multi-tier stacking.
Data Source
AI summary
A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.