3D Memory Staircase Contact Layout for Stress Misalignment
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Solution Overview
Problem
The manufacturing process of semiconductor memory devices can cause stress-induced deviations in the positional relationship of components, leading to operational issues and quality control challenges in three-dimensional nonvolatile memory devices due to the stacked structure of conductive and insulating layers.
Innovation Solution
The semiconductor memory device design includes a stacked body with alternately arranged conductive and insulating layers, featuring a staircase region with terraced word lines and select gate lines, and strategically positioned contacts that are adjusted to minimize the impact of stress-induced misalignment, ensuring proper electrical conduction and avoiding short-circuiting or leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked structure of conductive and insulating layers is used to increase storage capacity, then the storage density is improved, but stress-induced positional deviation among components occurs during manufacturing
Solution Approach 1:
The memory device is divided into multiple independent stacked bodies, each containing a complete set of conductive layers and insulating layers. This segmentation allows each stacked body to be manufactured and positioned independently, reducing the cumulative stress-induced deviation that would occur in a single large stacked structure.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture by vertically stacking multiple conductive layers and insulating layers. This dimensional change increases storage capacity while the independent positioning of each stacked body mitigates the positional deviation problem through spatial distribution.
2Productivity
If multiple conductive layers are stacked to increase memory density, then the storage efficiency is improved, but operational reliability deteriorates due to stress-induced misalignment
Solution Approach 1:
The patent designs the stacked structure with predetermined spacing and alignment features that compensate for expected stress-induced deviations. By anticipating and cushioning against potential misalignment before it affects operation, the reliability of the high-density stacked structure is maintained.
Solution Approach 2:
Different regions of the stacked structure are designed with locally optimized properties, such as varying the thickness or material composition of insulating layers in specific areas to compensate for stress-induced deviations. This local quality adjustment ensures that each region maintains proper electrical isolation and connection despite overall structural stress.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of first contacts arranged in a staircase region on one side in a second direction of a plate-like portion and along the plate-like portion, and individually connected to at least lower conductive layers among the plurality of terraced conductive layers in a first staircase portion; and a plurality of second contacts arranged in the staircase region on another side in the second direction of the plate-like portion and along the plate-like portion, and individually connected to the at least lower conductive layers in the first staircase portion, in which the plurality of first contacts is individually arranged at different positions in the second direction relative to the plate-like portion, depending on the positions in a first direction, and the plurality of second contacts is individually arranged at positions inverted in the second direction from the respective positions of the plurality of first contacts, with respect to the plate-like portion.