3D Memory Staircase Interconnections for Precise Contact Registration
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Solution Overview
Problem
Conventional methods for forming vertical memory arrays in non-volatile memory devices, such as NAND Flash memory, often result in undesirable structural configurations and damage due to off-center registration of top contacts, leading to inefficiencies in memory device fabrication.
Innovation Solution
A method involving a preliminary stack structure with alternating insulative and sacrificial materials, forming staircase structures and contact regions, followed by replacement gate processing to convert the sacrificial material into conductive material, and filling slots between blocks to create a stack structure with conductive and insulative tiers, enhancing electrical connectivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form vertical memory arrays, then memory device fabrication can proceed with standard processes, but off-center registration of top contacts occurs causing structural damage and undesirable configurations
Solution Approach 1:
The patent applies preliminary action by forming a preliminary stack structure with sacrificial materials and staircase structures before final contact formation. The sacrificial materials are strategically placed to guide subsequent processing steps, ensuring that contact structures are formed with proper alignment. This preliminary framework prevents off-center registration by establishing registration references early in the fabrication process, thereby maintaining both manufacturing precision and structural reliability.
Solution Approach 2:
The patent uses sacrificial materials as intermediary elements during the fabrication process. These sacrificial materials serve as temporary structures that facilitate precise contact formation and are later removed. The intermediary sacrificial structures provide physical references for alignment and prevent direct contact between potentially misaligned features, thus resolving the contradiction between manufacturing precision and structural integrity.
2Reliability
If staircase structures are formed to provide electrical access to conductive structures, then electrical connectivity is improved, but the complexity of the fabrication process increases
Solution Approach 1:
The patent segments the fabrication process into distinct modular steps: forming preliminary stack structures with sacrificial materials, creating staircase structures, forming contact structures, and finally removing sacrificial materials. Each segment is independently optimized and can be performed with standard processing techniques. This segmentation reduces overall process complexity while maintaining reliable electrical connectivity through the systematically formed staircase structures.
Solution Approach 2:
The staircase structures are formed in advance as preliminary features that simplify subsequent contact formation. By pre-establishing the stepped architecture that provides electrical access to conductive structures at multiple levels, the patent eliminates the need for complex simultaneous multi-level alignment processes, thereby improving electrical connectivity without proportionally increasing fabrication complexity.
3Quantity of substance
If memory density is increased using vertical memory array architectures, then the number of memory cells per die area increases, but the risk of structural damage during fabrication increases
Solution Approach 1:
The patent forms a preliminary stack structure with sacrificial materials that serves as a protective framework during high-density vertical array fabrication. This preliminary structure maintains mechanical stability and prevents structural damage while enabling increased memory cell density. The sacrificial materials act as internal supports that preserve structural integrity throughout the fabrication process, allowing vertical arrays to be packed more densely without compromising reliability.
Solution Approach 2:
The sacrificial materials function as beforehand cushioning by providing mechanical support and stress distribution during the fabrication of high-density vertical memory arrays. These preliminary structures absorb fabrication stresses and prevent damage to the delicate high-density architecture, enabling increased memory cell density while maintaining structural reliability throughout the manufacturing process.
Data Source
AI summary
A microelectronic device comprises a stack structure comprising blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers, at least one of the blocks comprising: a memory array region having vertically extending strings of memory cells within a horizontal area thereof; and a staircase region horizontally neighboring the memory array region. The staircase structure has steps comprising horizontal ends of the tiers; and a crest sub-region horizontally interposed between the staircase structure and the memory array region. A masking structure overlies the stack structure and has a different material composition than each of the conductive material and the insulative material. Filled slot structures are interposed between the blocks of the stack structure, at least one of the filled slot structures comprises at least one fill material that has an uppermost boundary vertically underlying an uppermost boundary of the masking structure.