3D Memory Staircase Structure for Higher Density Manufacturing
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to limitations in feature size, leading to increased manufacturing costs and reduced memory density.
Innovation Solution
A staircase structure for a 3D memory device is introduced, comprising a plurality of layer stacks with insulating and conductive materials, and landing pads formed over the conductive layers, which improves yield and manufacturing cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and circuit design, then memory density is improved, but manufacturing cost increases and fabrication becomes challenging
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to a three-dimensional staircase structure. The staircase structure includes multiple terraces at different heights, allowing memory cells to be arranged in vertical layers rather than just horizontal planes. This dimensional change enables continued memory density improvement without further reducing feature sizes, thereby avoiding the fabrication challenges and cost increases associated with extreme scaling.
2Quantity of substance
If feature sizes of memory cells are reduced to increase density, then memory density is improved, but manufacturing cost increases
Solution Approach 1:
By implementing a three-dimensional staircase architecture with multiple terraces, the patent achieves higher memory density through vertical stacking rather than horizontal scaling. This approach maintains larger, more manufacturable feature sizes while increasing capacity through the third dimension, thus avoiding the exponential cost increases typically associated with reducing feature sizes to the lower limit.
3Quantity of substance
If planar process techniques are used to scale memory cells, then memory density is improved, but process complexity and cost increase
Solution Approach 1:
The staircase structure is divided into multiple discrete terraces or steps, each representing a distinct fabrication stage. This segmentation allows the complex three-dimensional structure to be built incrementally through repeated deposition and etching cycles, making the manufacturing process more manageable and less complex than attempting to create the entire structure in a single planar process step.
Solution Approach 2:
The transition to three-dimensional staircase architecture with vertical terraces enables memory density improvement through structural complexity rather than process complexity. The vertical stacking approach simplifies the overall fabrication strategy compared to continued planar scaling, as it uses standard deposition and etching processes applied in sequence to build up the structure layer by layer.
Data Source
AI summary
A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.