3D Memory Staircase Structure With Dummy Stack Crack Control
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional structures lack stability and reliability, necessitating improved manufacturing methods and structures for enhanced operational reliability.
Innovation Solution
A semiconductor device with a dummy stack featuring alternating material layers, including a staircase structure and protrusions, and an insulating structure between the gate and dummy stack, along with a manufacturing method involving the formation of trenches and alternating material layers to create stable and reliable structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional stacking structure is adopted to improve integration density, then integration density is improved, but structural stability and reliability deteriorate
Solution Approach 1:
The device is divided into separate functional stacks (first stack with gate structure, second stack with dummy structure) connected by insulating structures. This segmentation allows each stack to be optimized independently for its function while maintaining overall structural stability through the connecting insulating structures, resolving the contradiction between high integration density and structural reliability.
Solution Approach 2:
Insulating structures serve as intermediary elements connecting the first stack and second stack. These intermediaries provide mechanical support and stress distribution, enhancing structural stability while enabling the three-dimensional stacked configuration that improves integration density.
2Productivity
If unit memory cell area is reduced to improve integration density, then integration density is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The invention transitions from two-dimensional planar memory cells to three-dimensional stacked structures. By utilizing the vertical dimension, multiple memory cells are stacked above each other, achieving high integration density without reducing the lateral area of individual memory cells, thus maintaining manufacturing precision.
3Productivity
If complex three-dimensional structures are implemented to improve integration density, then integration density is improved, but device complexity increases
Solution Approach 1:
The dummy stack is designed as a simplified copy of the functional stack, replicating the basic staircase structure and sidewall configuration. This copying approach allows the use of similar manufacturing processes for both stacks, reducing overall device complexity while achieving high integration density through three-dimensional stacking.
Data Source
AI summary
A semiconductor device includes a first gate structure including a first pad staircase structure and a first sidewall connected to the first pad staircase structure. The semiconductor device also includes a dummy stack including a dummy staircase structure and a first dummy sidewall connected to the dummy staircase structure, the first dummy sidewall including at least one first protrusion. The semiconductor device further includes a first insulating structure located between the first gate structure and the dummy stack.