3D Memory Staircase Layout for Dense Interconnect Routing
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Solution Overview
Problem
In stacked semiconductor memory devices, the increasing number of electrode film stacks complicates the layout of upper layer interconnects, making it difficult to integrate memory cells efficiently and increasing manufacturing costs.
Innovation Solution
A semiconductor memory device design featuring a staircase configuration for the end portion of the stacked body, with alternating regions of narrow and wide terraces, allows for easier connection of electrode films to transistors and reduces the complexity of interconnect layout by utilizing a staggered arrangement of contacts and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of electrode film stacks increases to enhance memory capacity, then storage density is improved, but the layout complexity of upper layer interconnects increases and manufacturing becomes more difficult
Solution Approach 1:
The stacked body is divided into multiple blocks, each with its own set of electrode films and memory cells. This segmentation allows the interconnect layout to be organized in a modular fashion, where each block can be independently routed, reducing overall layout complexity while maintaining high storage density through vertical stacking
Solution Approach 2:
The patent transitions from planar interconnect routing to three-dimensional routing by utilizing vertical vias and multiple interconnect layers that wrap around or pass through the stacked body. This dimensional change allows interconnects to access different electrode films at different heights, simplifying the routing problem while accommodating increased memory capacity
2Quantity of substance
If more electrode films are stacked vertically to increase storage density, then memory capacity is improved, but the chip surface area required for interconnect routing increases
Solution Approach 1:
Multiple interconnect layers are nested within each other, with lower layer interconnects positioned beneath upper layer interconnects. This nesting allows multiple signal paths to be routed in the same horizontal footprint by utilizing different vertical levels, thereby increasing storage density without proportionally increasing chip surface area
Solution Approach 2:
The interconnect structure employs dynamic routing where interconnect lines can change direction and layer at different points along their path. This allows the same horizontal area to serve multiple routing functions at different stages, reducing the total chip surface area needed while supporting high storage density through vertical stacking
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.