Memory Staircase Interconnect Layout to Reduce Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increased density and complexity of microelectronic devices, particularly in memory arrays, pose challenges in forming conductive interconnect structures due to the reduced spacing between neighboring conductive interconnects, leading to difficulties in adequate electrical communication with memory cells.
Innovation Solution
The design incorporates a staircase structure with multi-directional conductive paths and curved cross-sectional shapes in the staircase region, allowing for reduced area allocation and improved reliability, while also simplifying manufacturing processes by forming conductive structures in a single processing act, and mitigating capacitive coupling between neighboring conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between neighboring conductive interconnect structures is reduced to increase memory cell density, then the density of memory cells increases, but the difficulty of forming adequate electrical communication with memory cells increases
Solution Approach 1:
The patent introduces a third vertical dimension by forming conductive structures that extend vertically through multiple tiers of memory cells. This allows electrical communication to be established in the vertical direction rather than relying solely on horizontal spacing, enabling adequate signal transmission even when horizontal spacing between interconnect structures is reduced to increase cell density.
Solution Approach 2:
The conductive interconnect structures are segmented into multiple vertical portions that can be formed at different heights. This segmentation allows each segment to be optimized for specific electrical communication requirements, with lower segments providing broader coverage and upper segments providing more focused connections, thereby maintaining manufacturability while achieving high density.
2Ease of manufacture
If conventional straight conductive structures are used, then the manufacturing process is simpler, but the area usage efficiency and electrical conductivity are reduced
Solution Approach 1:
The patent employs curved conductive structures with rounded corners and arcuate paths instead of straight angular geometries. These curved structures provide smoother electrical field distribution, reduced capacitive coupling at corners, and more efficient area utilization. The curved design maintains manufacturability through standard deposition and etching processes while significantly improving area usage efficiency and electrical conductivity compared to conventional straight structures.
3Device complexity
If conventional angular conductive structures are used, then the design is simpler, but capacitive coupling between neighboring conductive structures increases
Solution Approach 1:
The curved conductive structures eliminate sharp angular corners that act as capacitive coupling hotspots. By using arcuate paths and rounded geometries, the electric field distribution is smoothed, reducing field concentration at corners and thereby minimizing capacitive coupling between neighboring conductive structures. This design maintains relatively simple fabrication processes while significantly reducing the harmful capacitive effects.
Data Source
AI summary
A microelectronic device comprises a stack structure comprising an array region comprising first conductive structures vertically spaced from one another, and a staircase region horizontally neighboring the array region and comprising second conductive structures vertically spaced from one another and coupled to the first conductive structures. The second conductive structures individually comprise portions extending in a first horizontal direction, and additional portions extending in a second horizontal direction transverse to the first horizontal direction. The staircase region comprises staircase structures having steps partially defined by edges of the second conductive structures. Some of the steps extend in the first horizontal direction and some others of the steps extend in the second horizontal direction. Related memory devices, electronic systems, and methods are also described.