3D Memory Cell Array Staircase Bonding for Single-Step Trimming
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Solution Overview
Problem
Existing semiconductor storage device manufacturing methods require multiple trimming steps, increasing complexity and reducing yield due to the need for precise substrate edge handling and potential damage during grinding processes.
Innovation Solution
A method involving bonding two semiconductor substrates with symmetrical memory cell array configurations, allowing for a single trimming step to form the semiconductor storage device, reducing the number of discarded memory cell arrays and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple trimming steps are used to manufacture semiconductor storage devices, then manufacturing precision can be maintained, but device complexity and process time increase
Solution Approach 1:
The patent combines multiple trimming operations into a single trimming step by designing the substrate structure to accommodate all necessary edge adjustments simultaneously. The substrate includes multiple regions with different patterns that can be trimmed in one operation, eliminating the need for sequential trimming steps while maintaining manufacturing precision.
Solution Approach 2:
The substrate is designed in advance with predetermined trimming regions and patterns that prepare the structure for a single trimming operation. By pre-configuring the substrate with all necessary edge features before trimming, the patent enables one-step trimming that achieves what would otherwise require multiple steps, reducing process complexity.
2Manufacturing precision
If multiple trimming steps are performed, then substrate edge precision can be achieved, but manufacturing time and labor costs increase
Solution Approach 1:
Multiple trimming operations are merged into a single trimming step by designing the substrate to include all necessary trimming regions that can be processed simultaneously. This consolidation maintains edge precision while significantly reducing the total time required for trimming operations and associated labor costs.
3Manufacturing precision
If substrates are trimmed before bonding, then edge alignment can be improved, but the number of discarded memory cell arrays increases
Solution Approach 1:
The substrate is designed with predetermined trimming regions that are optimized to maintain edge alignment while minimizing the loss of memory cell arrays. By carefully planning the trimming regions before fabrication, the patent enables precise edge alignment with reduced waste compared to conventional trimming approaches.
Solution Approach 2:
Different regions of the substrate are designed with different trimming characteristics. The substrate includes multiple regions with different patterns, allowing selective trimming in specific areas while preserving memory cell arrays in other regions. This local differentiation enables precise alignment without excessive discarding of functional arrays.
4Ease of manufacture
If conventional substrate processing is used, then manufacturing steps are straightforward, but step differences occur between memory cell array layers
Solution Approach 1:
The patent combines multiple processing steps including trimming, bonding, and flattening into an integrated process flow that eliminates step differences between layers. By coordinating these operations rather than performing them separately, the patent achieves layer flatness while maintaining manufacturing simplicity.
Solution Approach 2:
The substrate structure is designed in advance to accommodate bonding and subsequent flattening operations that will eliminate step differences. The predetermined design includes features that facilitate uniform bonding and enable the removal of step differences in a single flattening step, achieving layer flatness without complicating the manufacturing process.
Data Source
AI summary
A semiconductor storage device according to an embodiment includes a plurality of memory cell array layers. Each of the plurality of the memory cell array layers includes a plurality of memory cells. Each of the plurality of the memory cells includes a multi-layered body. The multi-layered body has a staircase structure including an inclined portion. The multi-layered body has a plurality of electrode layers having a plurality of end portions. The positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure. Two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween. The inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface.