3D Memory Staircase Column Structure to Prevent Stack Sagging
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Solution Overview
Problem
In semiconductor memory devices, particularly three-dimensional nonvolatile memory, the stacked body may sink or sag in the stacking direction due to shrinkage of insulating layers, leading to unevenness at the upper surface, which affects manufacturing processes like lithography and can result in defects such as polishing residues and insufficient breakdown voltage between word lines.
Innovation Solution
Incorporating a columnar portion with a structure that includes a dummy layer and flanged portions protruding towards the conductive layers, which supports the stacked body and maintains the breakdown voltage by reducing the risk of contact with plate-shaped contacts and preventing exposure of nitride layers during replacement processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the stacked body is formed with alternating conductive and insulating layers, then memory cells can be arranged three-dimensionally, but the insulating layers may shrink causing the stacked body to sink or sag, resulting in unevenness at the upper surface
Solution Approach 1:
The patent applies preliminary action by forming columnar portions with dummy layers and flanged portions before the insulating layers shrink. These structural elements are pre-positioned to provide support and prevent sinking or sagging of the stacked body during subsequent processing steps, thereby maintaining upper surface uniformity while enabling three-dimensional memory cell arrangement.
Solution Approach 2:
The patent employs composite materials by combining different insulating layer materials with distinct shrinkage characteristics. The first insulating layers have different shrinkage rates compared to the second insulating layers, allowing the flanged portions to protrude and provide mechanical support. This composite structure prevents stacked body collapse while maintaining the three-dimensional configuration of memory cells.
2Manufacturing precision
If the stacked body sinks or sags, then manufacturing processes like lithography are affected, but increasing structural support may increase device complexity
Solution Approach 1:
The patent applies segmentation by dividing the support structure into discrete columnar portions distributed at specific intervals within the stacked body. Each columnar portion contains segmented functional elements (dummy layer, flanged portions) that provide localized support. This segmented approach maintains manufacturing precision without requiring a uniformly complex structure throughout the entire device.
Solution Approach 2:
The patent implements local quality by providing enhanced structural support only in specific regions where columnar portions are formed, rather than uniformly throughout the entire stacked body. The flanged portions locally protrude to contact and support adjacent plate-shaped contacts at critical locations, maintaining lithography quality while minimizing overall device complexity.
3Productivity
If the pitch and cross-sectional area of columnar portions are reduced, then device density increases, but the breakdown voltage between word lines may be insufficient
Solution Approach 1:
The patent applies parameter changes by modifying the material composition and dimensional parameters of the insulating layers. The first insulating layers are configured with specific thicknesses and shrinkage rates that generate sufficient protruding flanged portions even when columnar portion pitch and cross-sectional area are reduced. This allows maintaining both high device density and adequate breakdown voltage through optimized material and geometric parameters.
Solution Approach 2:
The patent uses composite materials with different shrinkage characteristics to maintain breakdown voltage despite reduced columnar portion dimensions. The combination of first insulating layers with higher shrinkage and second insulating layers with lower shrinkage creates protruding flanged portions that provide electrical isolation. This composite approach enables reduced pitch and cross-sectional area while preserving the breakdown voltage required for reliable operation.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a stacked body with first conductive layers and first insulating layers alternately stacked. The stacked body includes a staircase portion in which the first conductive layers are in a staircase shape. A columnar portion extends in a stacking direction through the stacked body at the staircase portion. The columnar portion includes a semiconductor layer, a second insulating layer covering a side wall of the semiconductor layer, and a third insulating layer that covers the second insulating layer. The third insulating layer includes a material different from the second insulating layer and includes flanged portions that protrude from a sidewall thereof toward the first conductive layers at corresponding height positions.