Memory Staircase Structure With Supports to Prevent Stack Collapse
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Solution Overview
Problem
As vertical memory array technology advances, the stacks of conductive structures in non-volatile memory devices are prone to collapse during processing, reducing the reliability of memory strings and increasing parasitic capacitance due to decreasing feature dimensions.
Innovation Solution
The formation of sacrificial structures and support structures within the vertical memory array, which extend entirely through the stack structure, provides structural support and prevents tier collapse during processing, while also optimizing electrical connections to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the stacks increases to facilitate additional memory cells, then memory density is improved, but the stacks become prone to toppling or collapse during processing
Solution Approach 1:
The stack structure is divided into multiple tiers with insulative structures and conductive structures arranged in alternating layers. This segmentation provides internal support within the stack, preventing collapse while enabling increased height and memory density. The insulative structures act as structural dividers that maintain stack integrity during processing.
Solution Approach 2:
Sacrificial structures are formed within the stack structure before the replacement gate processing. These preliminary sacrificial structures provide structural support during subsequent processing steps, preventing tier collapse. The sacrificial structures are later removed and replaced with conductive structures to form the final memory device.
2Quantity of substance
If the dimensions and spacing of conductive features decrease, then memory density is improved, but parasitic capacitance between adjacent conductive features increases
Solution Approach 1:
The patent transitions from planar two-dimensional transistor arrangements to three-dimensional vertical memory array architectures. By stacking conductive and insulative structures vertically, the invention achieves higher memory density without proportionally increasing parasitic capacitance, as the vertical separation provides additional spacing between conductive features.
Solution Approach 2:
Insulative structures are positioned between adjacent conductive features and tiers within the stack. These insulative structures act as intermediaries that electrically isolate conductive elements, reducing parasitic capacitance between adjacent conductive features while allowing the features to be closely spaced for high density.
3Ease of operation
If staircase structures are formed to provide electrical access to conductive structures, then connectivity is improved, but the complexity of the device structure increases
Solution Approach 1:
The insulative structures serve multiple functions: they provide electrical insulation between conductive tiers, maintain structural integrity of the stack, and form the basis for staircase structures that provide electrical access. This multi-functionality reduces the need for separate dedicated structures, simplifying the overall device complexity while maintaining connectivity.
Data Source
AI summary
A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.