Semiconductor Memory Staircase Structure for Stress-Balanced Layer Stacks
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in maintaining yield and structural integrity during the manufacturing process due to asymmetrical stress caused by the replacement of sacrificial members, which can lead to layer stack incline and potential damage.
Innovation Solution
The semiconductor memory device employs a staircase structure with terrace portions in the contact area, where sacrificial members are partially removed via slits, and conductive layers are formed symmetrically to reduce stress, ensuring the layer stack remains stable and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sacrificial members are completely removed to form conductive layers, then electrical connectivity is achieved, but asymmetrical stress causes layer stack incline and structural damage
Solution Approach 1:
The patent applies asymmetry principle by intentionally creating a staircase structure with terrace portions at different heights in the contact area. This asymmetric design allows selective removal of sacrificial members from specific regions (first area) while retaining them in other regions (second area), thereby controlling stress distribution to prevent layer stack incline and structural damage during conductive layer formation
2Ease of manufacture
If sacrificial members are removed via wet etching, then conductive layers can be formed, but yield decreases due to structural damage
Solution Approach 1:
The patent applies local quality principle by differentiating the treatment of sacrificial members in different spatial regions. The first sacrificial members in the first area are removed to enable conductive layer formation, while the second sacrificial members in the second area are retained to maintain structural support. This localized selective removal approach enables successful conductive layer formation while preserving manufacturing yield by preventing widespread structural damage
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a substrate expanding in a first direction and a second direction, a plurality of conductive layers arranged in a third direction with a distance therebetween, the conductive layers including a first conductive layer, and each including a first portion and a second portion being arranged with the first portion in the second direction and including a terrace portion provided so as not to overlap an upper conductive layer in the third direction, a first insulating portion provided between the first portions and the second portions, and a first insulating layer arranged with the first portion of the first conductive layer in the second direction with the first insulating portion interposed therebetween.