Semiconductor Memory Device Staircase Configuration Surface Area Reduction
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Solution Overview
Problem
There is a need to reduce the device surface area of semiconductor memory devices to enhance efficiency and compactness.
Innovation Solution
The semiconductor memory device design incorporates multiple conductive layers with specific end portion configurations and alternating insulating layers, allowing for a staircase configuration that reduces the surface area by strategically positioning connecting bodies and memory portions, and a manufacturing method involving trench formation and staircase portion creation to achieve this design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar layout is used for conductive layers, then device surface area is large, but manufacturing process is simple
Solution Approach 1:
The patent transitions from a conventional planar two-dimensional layout to a three-dimensional stacked configuration where conductive layers are arranged vertically with alternating insulating layers. This dimensional change allows multiple conductive layers to occupy the same footprint area, significantly reducing the device surface area while maintaining electrical functionality through vertical stacking rather than horizontal expansion.
Solution Approach 2:
The patent implements a nested structure where multiple conductive layers are stacked vertically with insulating layers in between, creating a compact layered configuration. Each conductive layer is positioned at a different vertical level, allowing them to be nested within the same lateral footprint. This nesting approach enables high-density integration without increasing the device surface area.
2Area of stationary object
If staircase configuration with multiple conductive layers is implemented, then device surface area is reduced, but manufacturing precision requirement increases
Solution Approach 1:
The patent divides the conductive layers into multiple discrete segments with different lateral extents, creating a staircase configuration where each layer can be independently patterned. This segmentation allows precise control over the position and size of each conductive layer, enabling accurate alignment and positioning required for the reduced surface area design while maintaining manufacturability through step-by-step fabrication.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A portion of the second conductive layer is provided between the third conductive layer and a portion of the first conductive layer. The first conductive layer includes a first end portion crossing the first direction. The second conductive layer includes a second end portion crossing the first direction. The third conductive layer includes a third end portion crossing the first direction. A position in the first direction of a portion of the second end portion is between a position of the first end portion and a position of the third end portion. The position in the first direction of the portion of the second end portion is between a position of another portion of the second end portion and the position of the third end portion.