3D Memory Staircase Layout for Dense Via and Word Line Access
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges in maintaining efficient layout and access for memory devices, particularly in forming compact and space-efficient structures for contact vias and word lines.
Innovation Solution
The implementation of a memory device with a staircase-shaped region featuring zigzag configured word lines and alternating stacks of dielectric and conductive layers, allowing for a compact layout and efficient contact via placement, which is formed through a series of patterning processes and deposition methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional linear layouts are used for word lines and contact vias, then manufacturing and routing are simpler, but device density and space efficiency deteriorate
Solution Approach 1:
The patent transitions from conventional linear one-dimensional word line layouts to a two-dimensional staircase configuration. The word lines are arranged in multiple tiers or levels that step across the substrate, effectively utilizing vertical and lateral dimensions simultaneously. This dimensional transformation allows contact vias to be positioned at multiple elevation levels, dramatically increasing device density without proportionally increasing the footprint area.
Solution Approach 2:
The staircase structure implements a nested arrangement where word lines are organized in hierarchical levels. Lower-level word lines are positioned beneath upper-level word lines, creating a nested configuration similar to nested dolls. This nesting allows multiple word lines to occupy overlapping horizontal projections, maximizing the utilization of vertical space and improving integration density while maintaining manufacturability through sequential deposition processes.
2Quantity of substance
If feature sizes are reduced to increase integration density, then more components can be integrated, but manufacturing precision and control deteriorate
Solution Approach 1:
The patent segments the word line structure into discrete staircase steps or tiers, where each step represents a separable manufacturing unit. This segmentation allows the complex three-dimensional structure to be built incrementally through sequential deposition and patterning cycles. Each segment can be manufactured and controlled independently, reducing the cumulative precision requirements compared to forming the entire structure in a single process step, thereby improving manufacturability at reduced feature sizes.
3Area of stationary object
If compact staircase configurations are implemented, then space efficiency improves, but contact via placement and access become more difficult
Solution Approach 1:
The staircase configuration utilizes vertical dimensionality to resolve via access challenges. Contact vias are positioned at different elevation levels corresponding to different word line tiers, allowing simultaneous access to multiple word lines through vertically stacked via structures. This three-dimensional via arrangement maintains compact horizontal footprint while ensuring that no via is obscured by another, as each via targets a specific elevation level in the staircase hierarchy.
Data Source
AI summary
A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.