Semiconductor Memory Standby Current Failure Detection
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Solution Overview
Problem
The increasing integration density of semiconductor memory devices leads to higher probabilities of defects, resulting in standby current failures due to short-circuits, which are difficult to identify and rectify efficiently, causing excessive power consumption and yield reduction.
Innovation Solution
A semiconductor memory device with a test operation mode that selectively supplies power voltage to memory cells through a fuse-based system, allowing for the identification and isolation of defective rows or columns, thereby cutting off power to defective cells and preventing standby current failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integration density is increased to improve device functionality, then device capability is improved, but defect probability increases leading to standby current failures
Solution Approach 1:
The memory array is divided into multiple repair units, each with its own power supply control. This segmentation allows isolated identification and power cutoff of defective regions while maintaining operation of healthy regions, resolving the contradiction by enabling high integration density while managing defect risks through localized control.
Solution Approach 2:
A repair unit selection circuit and power supply control circuit are introduced as intermediary components between the memory array and power supply. These intermediaries enable selective power distribution to repair units, allowing the system to maintain high integration density while identifying and isolating defective cells that cause standby current failures.
2Productivity
If redundant memory cells are added to maintain high yield, then yield is improved, but device complexity increases
Solution Approach 1:
The power supply control circuit is merged with the repair unit selection circuit, allowing both functions to be implemented using shared control logic and selection signals. This merging reduces the overall complexity of the redundancy system while maintaining high yield through effective defect management.
Solution Approach 2:
The power supply control circuit serves multiple functions: it acts as a selection circuit for repair units, a power distribution switch, and a standby current suppression mechanism. This multi-functionality reduces the need for separate dedicated circuits, thereby maintaining low complexity while supporting redundancy for high yield.
3Reliability
If power voltage is continuously supplied to all memory cells, then memory operation is maintained, but standby current consumption increases due to defective cells
Solution Approach 1:
The power supply to memory cells is made dynamic rather than static. The power supply control circuit dynamically adjusts power distribution based on the operational status and defect identification of each repair unit. Healthy repair units receive power for normal operation, while defective units have power cutoff to eliminate standby current consumption, thus resolving the energy loss problem while maintaining memory operation reliability.
Solution Approach 2:
Different power supply conditions are applied to different regions (repair units) based on their local quality or health status. Healthy regions receive full power for operation, while defective regions receive no power to prevent standby current leakage. This localized quality-based power management resolves the contradiction between maintaining operation and reducing energy loss.
4Reliability
If defective rows or columns are replaced with redundant rows or columns, then defect coverage is improved, but identification process becomes complex
Solution Approach 1:
The memory array is segmented into repair units with dedicated selection circuits. This segmentation simplifies defect identification by allowing systematic testing and selection of individual repair units. The selection circuit can efficiently identify defective units through structured addressing and selection signals, reducing the complexity of defect detection while maintaining comprehensive defect coverage through redundancy.
Data Source
AI summary
A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecting the memory cells of the array in the repair unit in response to a row address in a test operation mode. A power switch circuit operates in response to the selection signals, and connects the second power line connected to the selected memory cells with the first power line in the test operation mode. The power switch circuit disconnects the remaining second power lines from the first power line.