Memory Standby Timing for Background Operation Completion

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Solution Overview

Problem

Memory systems face performance degradation due to incomplete background operations when entering standby mode, as they are abruptly isolated from voltage sources, disrupting ongoing maintenance tasks.

Innovation Solution

The memory system transmits an indication of duration to the host system upon receiving a standby command, allowing it to delay isolation and complete pending background operations before entering standby mode, thereby balancing power consumption and maintenance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the memory system enters standby mode immediately upon receiving a standby command, then power consumption is reduced, but background operations are interrupted and performance degrades

Engineering Contradiction:
Improvepower consumptionVSAvoidbackground operation completion
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The memory system performs preliminary actions by transmitting a duration indication to the host system before actually entering standby mode. This allows the host to delay voltage isolation until background operations are completed, ensuring operational integrity while still enabling power savings.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory system provides feedback to the host system through the duration indication mechanism. This feedback loop allows the host to adjust the standby timing based on ongoing background operations, creating a coordinated control mechanism that balances power consumption with operational reliability.

Inventive Principle:
Principle #23Feedback

2Reliability

If the memory system delays entry into standby mode to complete background operations, then operational reliability is maintained, but power consumption increases

Engineering Contradiction:
Improvebackground operation completionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the standby timing based on the duration of background operations. By making the standby entry point flexible rather than fixed, the system can optimize between completing necessary operations and reducing power consumption according to actual operational conditions.

Inventive Principle:
Principle #15Dynamics

3Loss of energy

If the host system isolates the memory system from voltage sources immediately upon standby command, then power savings are achieved, but ongoing maintenance tasks are disrupted

Engineering Contradiction:
Improvepower savingsVSAvoidmaintenance task completion
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The memory system takes preliminary action by notifying the host system of the expected duration of background operations before voltage isolation occurs. This allows the host to prepare for and coordinate the timing of voltage isolation with the completion of maintenance tasks, preventing disruption.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260064294A1Techniques for memory system standby mode control
Publication Date: 2026.03.05 MICRON TECHNOLOGY INC
  • US20260064294A1 patent drawing
  • US20260064294A1 patent drawing
  • US20260064294A1 patent drawing

AI summary

Methods, systems, and devices for memory system standby mode control are described. A system may be configured to support a memory system transmitting an indication of a duration to a host system in response to receiving a standby indication from the host system. For example, a memory system may determine a set of background operations to be performed at the memory system and, in response to a standby indication, may determine a duration associated with performing at least a subset of the set of background operations. In response to receiving the indication of the duration, the host system may delay an isolation of the memory system from one or more voltage sources, which may include the host system signaling an approval or a different duration to the memory system, during which the memory system may proceed with at least some of the determined set of background operations.