Memory Controller Status Pin Checking for Multi-Way Memory
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Solution Overview
Problem
In multi-way memory systems, checking the memory operation status of each device by a memory controller can limit input/output occupancy time, thereby reducing the overall performance of the memory system.
Innovation Solution
A memory system design that utilizes status input pins and chip enable pins to efficiently check the memory operation status of multiple devices, allowing for reduced I/O occupancy time by eliminating the need for separate status check commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory controller uses status check commands to check memory operation status, then the memory operation status can be obtained, but the I/O occupancy time increases and system performance decreases
Solution Approach 1:
The patent merges the status check function with the existing chip enable pin functionality. The chip enable pin is configured to serve dual purposes: enabling memory device operation and checking memory operation status. By combining these two functions into a single pin, the system eliminates the need for separate status check commands, thereby reducing I/O occupancy time while maintaining accurate status detection capability.
2Loss of information
If separate status check commands are used to check each memory device, then status information can be retrieved, but the number of commands increases and I/O resources are occupied excessively
Solution Approach 1:
The patent implements multi-functionality by configuring the chip enable pin to perform both memory device enabling and status checking functions. This universal approach allows a single pin to handle multiple tasks that would traditionally require separate dedicated pins or commands, thereby simplifying the command sequence and reducing I/O resource consumption while ensuring complete status information retrieval.
Data Source
AI summary
A memory system may include a plurality of first memory devices; and a memory controller that may include a first chip enable (CE) pin configured to output a first CE signal that enables selectively any one of the first memory devices and a first status input pin configured to receive a first output signal indicating a memory operation status of an enabled first memory device from among the first memory devices in a first memory operation status checking period. In the first memory operation status checking period, the first output signal has one of a first level to indicate a first status of the memory operation status of the enabled first memory device, a second level to indicate a second status of the memory operation status of the enabled first memory device, or a third level to indicate a disabled status of the first memory devices.