Semiconductor Memory Device Step Electrode Channel Resistance
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Solution Overview
Problem
In three-dimensionally arrayed semiconductor memory devices, it is challenging to form an impurity diffused layer for vertical channel transistors, limiting impurity concentration and thus increasing channel resistance between electrode layers, which restricts cell current.
Innovation Solution
The semiconductor memory device incorporates a stacked body with alternating electrode and insulating layers, featuring a step portion in the electrode layers to reduce channel resistance by minimizing the distance between electrode layers, and includes a channel body and memory film that penetrate this step portion, allowing for a lower resistance channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertical channel transistor structure is adopted in three-dimensionally arrayed memory devices, then the channel resistance between electrode layers is reduced, but it becomes difficult to form an impurity diffused layer and increase impurity concentration
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical channel structure that extends through the stacked body in the stacking direction. This dimensional change allows the channel to pass through multiple electrode layers, reducing the effective channel resistance between layers while maintaining the ability to form impurity diffused layers through vertical ion implantation or diffusion processes.
Solution Approach 2:
The patent changes the channel orientation from horizontal to vertical, and modifies the impurity distribution profile to accommodate the vertical structure. By adjusting the doping parameters (concentration, depth, distribution) along the vertical axis, the patent achieves low channel resistance while maintaining manufacturability through standard semiconductor processing techniques.
2Reliability
If the distance between electrode layers is reduced to increase cell current, then the channel resistance decreases, but the insulation between layers becomes more challenging
Solution Approach 1:
The patent employs composite insulating structures between electrode layers, combining multiple materials with complementary properties (e.g., high-k dielectrics, low-k materials, or stacked dielectric layers) to achieve sufficient insulation performance at reduced spacing. This allows closer electrode layer spacing while maintaining electrical isolation.
Solution Approach 2:
The patent addresses the insulation challenge by extending the channel and insulating structures vertically through the stacked body, using the third dimension to provide adequate insulation paths even when lateral spacing is reduced. The vertical orientation allows insulation to be achieved through layer thickness rather than lateral separation.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a lower gate layer, a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer, a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer, and a memory film provided between the electrode layer and the channel body. The memory film includes a charge storage film. The electrode layer includes a step portion in which a step is formed in a stacking direction of the stacked body. The channel body and the memory film pass through the step portion.