Semiconductor Memory Stepped Structure Contact Wiring
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Solution Overview
Problem
Current semiconductor memory devices with staircase structures face challenges in manufacturing efficiency and complexity due to the alternation of conductive and insulating layers, which affects the formation of accurate contact connections and the overall structure integrity.
Innovation Solution
The semiconductor memory device employs a staircase structure with conductive layers and insulating layers alternately stacked on a substrate, where the end parts of the conductive layers recede, and contact wirings are formed to connect with the extended portions of the conductive layers, enabling efficient electrical insulation and connection, and a method involving sacrificial layers and etching processes to create the staircase structure and contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive and insulating layers are alternately stacked to form a staircase structure, then electrical insulation between layers is improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
A sacrificial insulating layer is formed preliminarily between the conductive layers during the stacking process. This sacrificial layer is later removed through etching to create contact holes, eliminating the need for complex sequential insulation processes and simplifying the overall manufacturing workflow while maintaining electrical insulation integrity.
Solution Approach 2:
The sacrificial insulating layer serves as an intermediary element that facilitates the formation of contact holes between conductive layers. By introducing this temporary medium layer, the patent enables simpler etching-based contact hole creation rather than requiring complex direct patterning through multiple insulating layers.
2Reliability
If contact wirings are formed to connect extended portions of conductive layers, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The conductive layers are formed with extended portions that protrude beyond the insulating layers in advance. This preliminary extension creates built-in contact pads that simplify subsequent wiring formation, reducing the precision requirements for contact hole alignment and connection while ensuring reliable electrical connectivity.
3Adaptability or versatility
If staircase structure is implemented with multiple alternating layers, then device functionality is improved, but production time and manufacturing steps increase
Solution Approach 1:
Multiple functional layers (conductive layers, insulating layers, and sacrificial insulating layers) are combined into a single integrated staircase structure through alternating deposition. This merging approach enables simultaneous formation of multiple functional elements in one manufacturing sequence, reducing total production time while maintaining full device functionality.
Solution Approach 2:
The sacrificial insulating layers are incorporated preliminarily during the layer stacking process itself, rather than being added as separate post-processing steps. This preliminary integration allows for more efficient batch processing and reduces the total number of discrete manufacturing steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, enhances the structural integrity of the memory cell array, and improves the electrical connectivity between layers, thereby increasing the reliability and efficiency of the semiconductor memory device.
Implementation Method 1
contact holes are formed by removing the sacrificial insulating layers
Data Source
AI summary
A semiconductor storage device includes a substrate, a stack of first insulating layers and conductive layers that are alternately formed on the substrate in a memory region and a peripheral region and electrically insulated from each other, a second insulating layer covering the stack of the first insulating layers and the conductive layers in the peripheral region, and a plurality of contact wirings formed in the peripheral region, each contact wiring extending from an upper surface of the second insulating layer towards the substrate and electrically connected to a corresponding one of the conductive layers. In the peripheral region, each conductive layer has an extended portion that covers side and upper surfaces of an end portion of a first insulating layer that is formed immediately thereabove, and each contact wiring is in direct contact with the extended portion of the corresponding conductive layer.