Memory Interconnect Stepped Structure With Continuous Reference Pattern
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in managing the position of stepped structures in stacked interconnects during manufacturing, leading to potential short circuits and decreased yield due to misalignment, and the use of isolated reference patterns can cause dust generation and reduce chip area efficiency.
Innovation Solution
The semiconductor memory device employs a stadium-shaped stepped structure with continuous reference patterns within the contact areas to accurately measure and adjust the position of stepped parts, reducing dust generation and improving yield by integrating these patterns into the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If isolated reference patterns are used to measure stepped structure positions, then measurement capability is provided, but dust generation increases and chip area efficiency decreases
Solution Approach 1:
The reference pattern is merged with the stepped structure of the interconnect itself. The continuous reference pattern forms an integral part of the stacked interconnect structure, eliminating the need for separate isolated reference patterns. This integration prevents dust generation from isolated patterns while maintaining measurement capability through the continuous reference structure.
Solution Approach 2:
The stacked interconnect structure serves multiple functions: it acts as both the electrical interconnect and the reference pattern for measurement. The continuous reference pattern within the interconnect structure provides measurement capability while the interconnect itself performs its electrical function, eliminating the need for separate reference elements that would generate dust.
2Measurement precision
If isolated reference patterns are used, then measurement capability is provided, but chip area efficiency decreases
Solution Approach 1:
The reference pattern measurement function is merged into the interconnect structure itself. The continuous reference pattern is formed as part of the stacked interconnect, eliminating the need for separate isolated reference patterns that would consume additional chip area. This integration improves chip area efficiency while maintaining measurement capability.
3Device complexity
If stepped structures in stacked interconnects are not precisely controlled, then manufacturing complexity is reduced, but short circuits occur and yield decreases
Solution Approach 1:
The continuous reference pattern provides a basis for measuring and controlling the position of stepped structures during manufacturing. By using the interconnect structure itself as the reference, real-time measurement and adjustment of stepped structure positions can be performed, providing feedback control to prevent misalignment and short circuits while maintaining manufacturing feasibility.
4Area of stationary object
If continuous reference patterns are integrated into interconnect structure, then chip area efficiency improves and dust generation is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The stacked interconnect structure with continuous reference pattern serves itself as the measurement standard. The interconnect structure provides its own reference for position measurement, eliminating the need for external isolated reference patterns. This self-service approach integrates the measurement function into the structure itself, improving chip area efficiency while the continuous nature of the reference pattern facilitates accurate measurement and control during manufacturing.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a substrate, conductive layers, pillars, and contacts. The substrate includes first and second areas, and block areas. The conductive layers are divided for each of the block areas. The conductive layers includes terraced portions. The contacts are respectively provided on the terraced portions for each of the block areas. The second area includes a first sub area and a second sub area. The first sub area includes a first stepped structure. The second sub area includes a second stepped structure and a first pattern. The first pattern is continuous with any one of the conductive layers. The first pattern is arranged between the first stepped structure and the second stepped structure.