Memory Storage Device Data Writing Method for Error Correction

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Solution Overview

Problem

Current data writing methods for non-volatile memory modules face challenges in error checking and correcting capability, algorithm complexity, hardware costs, and data access time due to limited bits in encoded data and format mismatches between physical programming units.

Innovation Solution

A data writing method that increases the number of bits in encoded data by distributing data across multiple physical programming units within the same physical erasing unit, using multi-frame encoding and concatenated information to record locations, and storing encoded data in a separate unit, ensuring identical formats and reduced complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of bits of the encoded data of the multi-frame encoding is increased to improve error checking and correcting capability, then the error checking and correcting capability is improved, but the complexity in algorithm design and costs in hardware design may be increased

Engineering Contradiction:
Improveerror checking and correcting capabilityVSAvoidcomplexity in algorithm design and costs in hardware design
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the encoded data into multiple segments, each stored in a separate physical programming unit. The original data is segmented into i segments stored in i first physical programming units, while the encoded data is stored in a second physical programming unit. This segmentation allows the system to achieve high error checking and correcting capability without requiring a single large complex encoding structure, thereby reducing algorithmic complexity and hardware costs.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If the format of the physical programming unit for storing data written by a host system is different from a format of the physical programming unit for storing the encoded data of the multi-frame encoding, then the flexibility in data storage is improved, but complexity in algorithm design and costs in hardware design may both be increased

Engineering Contradiction:
Improveflexibility in data storageVSAvoidcomplexity in algorithm design and costs in hardware design
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent employs a universal data structure format that can accommodate both host system data and encoded multi-frame data. By using a unified format with flexible field definitions, the system achieves adaptability for different data types while avoiding the need for complex format conversion algorithms and multiple specialized hardware components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If the encoded data of the multi-frame encoding is stored in a physical erasing unit and the physical erasing unit is different from a physical erasing unit where the data written by the host system are located, then the data organization flexibility is improved, but the time for writing and reading the encoded data of the multi-frame encoding may be increased

Engineering Contradiction:
Improvedata organization flexibilityVSAvoidtime for writing and reading the encoded data
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges the storage of original data and encoded data within the same physical erasing unit. By locating the second physical programming unit (storing encoded data) within the same physical erasing unit as the i first physical programming units (storing original data), the system achieves fast data access and writing operations while maintaining flexible data organization. This eliminates the need for cross-erasing-unit access, significantly reducing write and read times.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10922019B2Data writing method, memory controlling circuit unit and memory storage device
Publication Date: 2021.02.16 PHISON ELECTRONICS
  • US10922019B2 patent drawing
  • US10922019B2 patent drawing
  • US10922019B2 patent drawing

AI summary

A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data from a host system, and writing the data into a plurality of first physical programming units; performing a multi-frame encoding according to the plurality of data to generate encoded data, and writing the encoded data into a second physical programming unit; and writing a plurality of first concatenated information related to the encoded data into the plurality of first programming units, respectively.