Memory Storage Parity Distribution Across Chip-Enabled Regions
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Solution Overview
Problem
Existing multi-physical unit encoding mechanisms in rewritable non-volatile memory modules waste bandwidth by storing parity data in a specific plane or chip enabled region, leading to inefficient utilization of available channels.
Innovation Solution
The proposed method involves storing target data and its corresponding parity data in different physical management units across multiple chip enabled regions, ensuring that the parity data is dispersedly stored in distinct chip enabled regions to improve channel utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity data is stored in a specific plane or chip enabled region, then encoding can be performed using multi-physical unit mechanisms, but bandwidth is wasted and channel utilization is inefficient
Solution Approach 1:
The patent segments the storage of data and parity data by placing them in different physical management units. Specifically, data is stored in a first physical management unit while its corresponding parity data is stored in a second physical management unit, allowing independent access and optimization of each segment, thus improving bandwidth utilization while maintaining data protection.
Solution Approach 2:
The patent transitions from storing data and parity data within the same plane or chip enabled region to distributing them across different chip enabled regions. This dimensional redistribution allows parallel access through multiple channels, transforming the storage architecture from a single-dimension constraint to a multi-dimensional layout that maximizes bandwidth utilization.
2Device complexity
If parity data is stored in the same chip enabled region as data, then storage organization is simplified, but channel utilization is reduced and bandwidth is wasted
Solution Approach 1:
The patent divides the storage system into separate physical management units for data and parity data. This segmentation is managed through mapping tables that track the location of data and its corresponding parity data, organizing complexity in the control layer while enabling parallel channel access at the physical layer, thus resolving the contradiction between organization simplicity and channel utilization.
Solution Approach 2:
The patent introduces mapping tables as an intermediary mechanism to manage the distributed storage of data and parity data. These mapping tables store location information that enables the system to efficiently track and access data across different chip enabled regions without requiring complex direct management, thus maintaining organizational simplicity while achieving high channel utilization.
3Productivity
If data and parity data are stored in different physical management units across chip enabled regions, then bandwidth utilization is improved, but access complexity increases
Solution Approach 1:
The patent uses mapping tables as intermediary structures that store location information for data and parity data across different chip enabled regions. This intermediary layer abstracts the complexity of distributed storage, allowing the system to maintain simple access patterns while achieving high bandwidth utilization through parallel channel operations.
Solution Approach 2:
The mapping table structure serves multiple functions: it tracks data locations, manages parity data placement, and enables efficient access patterns. This multi-functional design consolidates the complexity management into a single versatile mechanism, reducing overall system complexity while maintaining high bandwidth utilization across multiple channels.
Data Source
AI summary
A data storage method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving at least one write command instructing to store target data from a host system; encoding the target data to generate parity data; and respectively storing the target data and the parity data in a first physical management unit and a second physical management unit, and each of the first physical management unit and the second physical management unit crosses multiple chip enabled (CE) regions. In addition, in the first physical management unit, first data is stored in a first chip enabled region among the chip enabled regions. In the second physical management unit, first parity data for protecting the first data is stored in a second chip enabled region among the chip enabled regions, and the first chip enabled region is different from the second chip enabled region.