3D Memory Strapping Structure for IR Drop Reduction
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Solution Overview
Problem
In a 3D array of memory cells, achieving low-resistance conductive lines is challenging due to limited space, making it difficult to minimize IR drop and its impact on threshold voltage variation.
Innovation Solution
A memory structure with a 3D array of memory cells, including first and second conductive lines, a top metal plate, and a strapping structure with connecting and jumping lines, where the strapping structure is configured on dummy regions to redirect current from first conductive lines to the top metal plate, reducing resistance and IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of common source line is increased to reduce resistance, then the resistance decreases, but in 3D array structure the available space is limited and cannot accommodate wider lines
Solution Approach 1:
The patent transitions from 2D to 3D architecture by stacking multiple layers of conductive lines (first conductive lines, second conductive lines, top metal plate) vertically. This multi-layer approach allows current to flow through multiple parallel paths in the vertical dimension, effectively reducing resistance without increasing the footprint area of individual conductive lines.
Solution Approach 2:
The conductive path is segmented into multiple components: first conductive lines in a first direction, second conductive lines in a second direction (different from first), and a top metal plate. This segmentation creates multiple current pathways that work together to reduce overall resistance while fitting within the limited 3D space.
2Reliability
If the width of conductive line is increased to minimize IR drop, then the IR drop decreases, but the geometric size modification is difficult in 3D array structure
Solution Approach 1:
Instead of modifying the width (horizontal dimension) of conductive lines, the patent utilizes the vertical dimension by introducing multiple stacked layers of conductive structures. The first conductive lines, second conductive lines, and top metal plate are arranged in different vertical levels, creating parallel current paths that reduce IR drop without requiring geometric size modification of individual lines.
Solution Approach 2:
The current path is divided into multiple segments across different layers and directions. The first conductive lines extend in a first direction, second conductive lines extend in a second direction, and the top metal plate provides additional parallel pathways. This segmentation distributes the current load across multiple segments, reducing IR drop without complex geometric modifications.
Data Source
AI summary
A memory structure includes a 3D array of memory cells, a plurality of first conductive lines disposed on the 3D array, a plurality of second conductive lines disposed on the first conductive lines, a top metal plate disposed on the second conductive lines, and at least one strapping structure. The second conductive lines and the first conductive lines extend on different directions. The at least one strapping structure is configured for the first conductive lines and correspondingly disposed on at least one dummy region of the 3D array. Each strapping structure includes a connecting structure and a jumping line. The jumping line is disposed on and coupled to the connecting structure, and coupled to the top metal plate. The jumping line and the second conductive lines extend on the same direction.