Memory Encryption via Separate Stream Ciphers

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Solution Overview

Problem

Current computer memory systems face challenges in securely protecting data and instructions shared between memory controllers and memory, particularly in ensuring the integrity and confidentiality of data and addresses, which is essential for proprietary information and complex applications.

Innovation Solution

The implementation of separate stream ciphers for write and read channels using shared security resources, including link-pad generators and encryptors/decryptors, to encrypt and decrypt data and addresses, ensuring secure communication and preventing unauthorized access by using synchronized pad values for each memory transaction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate stream ciphers are implemented for write and read channels, then data security and confidentiality are improved, but device complexity increases due to requiring separate encryptors/decryptors and synchronized pad value generation for each channel

Engineering Contradiction:
Improvedata securityVSAvoidencryption circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The encryption system is segmented into separate write and read channels, each with its own stream cipher instance. This segmentation ensures that encryption operations for writes and reads are independent and can be performed simultaneously without interference, thereby improving data security while managing complexity through modular organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A single pad value generator is designed to serve multiple functions by generating synchronized pad values for both write and read channels. This multi-functional approach reduces device complexity by eliminating the need for completely separate pad value generation circuits while maintaining the security requirements of both channels

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If synchronized pad values are used for each memory transaction, then encryption reliability is improved, but processing time may increase due to the overhead of maintaining synchronization between separate stream ciphers

Engineering Contradiction:
Improveencryption reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The pad value generator operates continuously to maintain synchronized pad values for both write and read channels. This continuous operation ensures that encryption reliability is preserved without interruption, while the synchronized nature of the generation process minimizes processing overhead by avoiding repeated synchronization operations

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

A control mechanism acts as an intermediary to coordinate pad value generation between the write and read stream ciphers. This intermediary ensures that pad values remain synchronized across both channels, maintaining encryption reliability while optimizing processing time through coordinated operation

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9465961B2Methods and circuits for securing proprietary memory transactions
Publication Date: 2016.10.11 RAMBUS INC
  • US9465961B2 patent drawing
  • US9465961B2 patent drawing
  • US9465961B2 patent drawing

AI summary

Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.