Memory Stress Testing via Local Bit Line Segmentation
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Solution Overview
Problem
Conventional stress testing methods for memory devices often fail to detect multiple short circuits simultaneously and can be interrupted by a single detected short circuit, limiting their effectiveness and efficiency.
Innovation Solution
A memory device and stress testing method that program memory cells to specific digital states, couple local bit lines to a global bit line or ground based on these states, apply a stress voltage, and sense the states after a predetermined time, allowing for the detection of multiple short circuits without interruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional stress testing methods are used, then the testing process can be simple, but the detection capability for multiple short circuits is limited and the test may be interrupted by a single detected short circuit
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block having its own set of local bit lines. The testing process segments the detection of short circuits by block, allowing multiple short circuits to be detected independently without interrupting the overall test. Each block can be tested separately while other blocks continue testing, enabling parallel detection across the memory device.
Solution Approach 2:
Global bit lines serve as intermediaries that connect multiple local bit line groups from different blocks. By coupling selected local bit lines to global bit lines based on predetermined patterns, the system can detect short circuits across multiple blocks simultaneously through the global bit lines without requiring direct intervention in each local block, thus maintaining test continuity.
2Reliability
If the stress testing process stops when a short circuit is detected, then the testing reliability is improved, but the productivity and efficiency of the testing process deteriorates
Solution Approach 1:
The memory device is divided into multiple independently testable blocks. When a short circuit is detected in one block, the testing can continue in other blocks without interruption. This segmentation allows the system to maintain high productivity by testing multiple blocks in parallel while ensuring reliability through comprehensive detection across all blocks.
Solution Approach 2:
The stress testing process applies stress voltages continuously across multiple blocks simultaneously. By using global bit lines to couple multiple local bit line groups, the testing action continues uninterrupted across the entire memory device, detecting multiple short circuits in a single continuous test rather than stopping at the first detection.
3Measurement precision
If multiple local bit lines are coupled to the global bit line, then the detection coverage is improved, but the complexity of bit line management increases
Solution Approach 1:
Global bit lines are designed to serve multiple functions: they connect to local bit lines from multiple different blocks, carry stress voltages, and enable detection of short circuits across numerous memory cell locations simultaneously. This multi-functionality allows a single global bit line to manage complexity by consolidating connections that would otherwise require multiple separate testing paths.
Data Source
AI summary
A memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines extending in a row direction and coupled to respective rows of the memory cells, and a plurality of local bit lines extending in a column direction and coupled to respective columns of the memory cells. The control unit is configured to program a selected one of the rows of memory cells to have a predetermined pattern of digital states, couple selected ones of the local bit lines to a global bit line and couple unselected ones of the local bit lines to ground based on the predetermined pattern, apply a stress voltage to the global bit line, and after a predetermined period of time, sense the digital states of the selected row of memory cells.