Memory String Compensation Cells for Read Current Accuracy
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Solution Overview
Problem
In 3D NAND flash memory circuits, string resistance causes accuracy issues during multiply-and-accumulation operations, leading to inaccuracies in inference and classification tasks, and increasing overdrive voltage to mitigate this introduces read disturb in unselected cells.
Innovation Solution
A memory device with compensation cells that adjust read current by applying compensation voltages based on the number of programmed cells, using multiple compensation cells per string to maintain current accuracy and reduce string resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If overdrive voltage is increased to reduce unselected cell resistance, then string resistance is mitigated, but read disturb occurs in unselected cells
Solution Approach 1:
The patent introduces compensation cells as intermediary elements that mediate between the read operation and the unselected memory cells. These compensation cells receive controlled overdrive voltage to adjust string resistance, while being isolated from the main memory array through separate bit lines, thus preventing read disturb to unselected cells while still improving computation accuracy
Solution Approach 2:
The patent segments the memory array into computation regions and compensation regions. Compensation cells are separated from synaptic cells and connected through dedicated compensation bit lines, allowing independent voltage control. This segmentation enables applying overdrive voltage selectively to compensation cells without affecting unselected synaptic cells, resolving the read disturb issue while maintaining computation accuracy
2Measurement precision
If compensation cells are added to each string, then read current accuracy is improved, but device complexity and vertical layers increase
Solution Approach 1:
The patent designs compensation cells to serve multiple functions: they compensate for string resistance variations, provide read current accuracy, and can be programmed to different threshold voltage levels to handle different numbers of programmed synaptic cells. This multi-functionality reduces the need for additional compensation circuits and vertical layers, as each compensation cell can adapt to various computation scenarios
Solution Approach 2:
The patent varies the threshold voltage parameter of compensation cells based on the number of programmed synaptic cells in each string. By programming compensation cells with different threshold voltage levels, the system can accurately compensate for string resistance without requiring a fixed number of compensation cells per string, thus reducing device complexity and vertical layer requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for variations in read currents, improving computation accuracy in neural networks by reducing string resistance and minimizing the need for additional layers, thus enhancing performance and reducing costs.
Implementation Method 1
the at least one compensation cell in each of the strings has a resistance responsive to at least one compensation voltage applied on the at least one compensation cell to adjust a read current
Data Source
AI summary
A memory device is provided and includes a memory array. The memory array includes multiple strings, each of the strings including multiple memory cells and at least one compensation cell that are coupled in series to a corresponding one of multiple bit lines. In a read operation, the at least one compensation cell in each of the strings has a resistance responsive to at least one compensation voltage applied on the at least one compensation cell to adjust a read current in the corresponding bit line to a current value. The resistance is associated with a number of programmed cells in the memory cells coupled to the corresponding bit line.