3D Memory Array String Contacts With Selective Silicon Deposition

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Solution Overview

Problem

Current memory array fabrication methods face challenges in minimizing undesired etching and ensuring precise electrical coupling between channel material strings and conductor tiers, which can affect the reliability and efficiency of memory cell formation.

Innovation Solution

The method involves forming a conductor tier with alternating insulative and conductive tiers, where channel-material strings extend through these tiers, and conducting material is deposited in the lower conductive tier to electrically couple with the channel material, using selectively deposited silicon to enhance conductivity while minimizing etching encroachment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional etching methods are used to form memory cells, then manufacturing process is simpler, but undesired etching encroachment occurs reducing reliability

Engineering Contradiction:

Improvememory cell formation reliabilityVSAvoidundesired etching encroachment

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A sacrificial material layer is introduced as an intermediary between the etching process and the conductor tier. This sacrificial layer protects the conductor tier from undesired etching encroachment while allowing precise formation of contact holes through controlled etching of the sacrificial material itself.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial material layer is deposited beforehand to define the precise location and depth of contact holes before the actual etching of conductor material occurs. This preliminary action prevents over-etching and encroachment into adjacent structures.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If conducting material is deposited to electrically couple channel material and conductor tier, then electrical coupling is improved, but process complexity increases

Engineering Contradiction:

Improveelectrical coupling reliabilityVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial material layer serves multiple functions: it defines contact hole locations, protects underlying structures during etching, and provides a template for conducting material deposition. This self-service approach simplifies the overall process by combining multiple functions in a single layer.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The method employs selective deposition parameters to deposit conducting material only in specific regions where contact holes are formed. By controlling deposition conditions, the process achieves precise electrical coupling without requiring additional complex patterning steps.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If silicon is selectively deposited to enhance conductivity, then electrical performance is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveelectrical conductivityVSAvoiddeposition precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The sacrificial material layer acts as a precise template that guides silicon deposition. By depositing silicon selectively on this template, the method achieves high precision in controlling where conductive material is formed, reducing the actual deposition precision requirements compared to direct deposition on the substrate.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces undesired etching and improves the electrical coupling between channel material strings and conductor tiers, enhancing the reliability and efficiency of memory cell formation in memory arrays.

Implementation Method 1

Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface

Methodology Applied

Scientific EffectSelective deposition: Deposition (physical)

Data Source

PatentUS20230397420A1Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

Publication Date: 2023.12.07 MICRON TECHNOLOGY INC

AI summary

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tier. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface. Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface. Other embodiments, including structure independent of method, are disclosed.