3D Memory Array String Coupling With Dopant Barrier Layers
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Solution Overview
Problem
Current memory array fabrication methods face challenges in minimizing undesired etching and ensuring precise electrical coupling of channel material strings with conductor tiers, which can lead to inefficiencies in forming reliable memory cells.
Innovation Solution
The method involves forming a conductor tier on a substrate with laterally-spaced memory-block regions comprising alternating conductive and insulative tiers, where channel-material strings extend through these tiers, and conducting material is formed in the lower tiers to electrically couple with the channel material, using conductively-doped semiconductive material and intermediate layers of different compositions to enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate-last or replacement-gate processing is used to form memory cells, then manufacturing flexibility and device performance are improved, but undesired etching of materials occurs during the formation process
Solution Approach 1:
A sacrificial layer is introduced as an intermediary material between the channel material and the gate electrode. This sacrificial layer protects the channel material from undesired etching during gate formation processes while enabling manufacturing flexibility. The sacrificial layer is temporarily present during fabrication and is subsequently removed, having served its protective function.
Solution Approach 2:
The sacrificial layer is formed in advance before the gate electrode deposition. This preliminary action establishes a protective barrier that prevents etching damage to the channel material during subsequent gate formation steps, allowing the gate-last or replacement-gate processing to proceed without compromising channel material integrity.
2Device complexity
If conventional fabrication methods are used, then manufacturing simplicity is maintained, but undesired etching affects the integrity and performance of memory cells
Solution Approach 1:
The sacrificial layer acts as a mediator that temporarily protects the channel material during conventional fabrication processes. By introducing this intermediate protective layer, the method maintains the simplicity of conventional fabrication sequences while significantly improving memory cell integrity and performance by preventing etching damage.
Solution Approach 2:
The sacrificial layer provides beforehand cushioning or protection to the channel material against etching attacks. This prior protective measure ensures that even when using conventional fabrication methods, the channel material remains intact and the memory cells achieve reliable performance.
3Reliability
If dopants are introduced to enhance conductivity in memory cell regions, then electrical performance is improved, but dopant migration occurs which destabilizes the memory cell structure
Solution Approach 1:
A barrier layer is introduced as an intermediary between regions with different dopant concentrations. This barrier layer prevents the migration of dopants from highly doped regions to adjacent regions, thereby maintaining electrical performance while stabilizing the compositional integrity of the memory cell structure.
Solution Approach 2:
The barrier layer extracts or removes the harmful effect of dopant migration by providing a physical and chemical barrier. By taking out the migration pathway, the barrier layer allows dopants to remain in their intended locations, ensuring both electrical performance and structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes undesired etching and ensures robust electrical coupling, improving the formation of memory cells by using conductively-doped semiconductive material and intermediate layers to facilitate efficient electrical connections within the memory array.
Implementation Method 1
forming conductively-doped semiconductive material in the lower first tier against the channel material of the individual channel-material strings
Implementation Method 2
incorporating an intermediate material to prevent upward migration of conductivity-enhancing dopants, thereby stabilizing the memory cell structure
Data Source
AI summary
A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, re disclosed.