Memory String Gate Layout for Faster Word Line Boosting
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in improving processing capability and reducing power consumption during read and program operations due to shared word lines and selection transistors, which lead to reduced boosting speed and increased current consumption.
Innovation Solution
The semiconductor memory device configuration includes separate selection gate lines for each memory cell array, allowing non-selected string units to have their selection transistors turned on and channel potentials set higher than selected units, utilizing capacitive coupling to enhance word line boosting speed and reduce current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shared word lines and selection transistors are used in existing semiconductor memory devices, then device complexity is reduced, but processing capability and power consumption are deteriorated
Solution Approach 1:
The patent divides the memory device into multiple independent memory cell arrays (first memory cell array and second memory cell array), each with its own dedicated selection gate lines and selection transistors. This segmentation allows parallel operation of different string units, improving processing capability while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent introduces separate selection gate lines (first selection gate lines and second selection gate lines) for different memory cell arrays, adding a dimensional separation to the selection mechanism. This enables independent control and parallel boosting of word lines in different arrays, enhancing processing capability without significantly increasing overall device complexity.
2Use of energy by stationary object
If shared word lines and selection transistors are used in existing semiconductor memory devices, then device complexity is reduced, but power consumption is increased
Solution Approach 1:
The patent segments the selection mechanism into separate selection transistors and selection gate lines for each memory cell array. This allows non-selected arrays to have their selection transistors turned off, reducing leakage current and power consumption, while the segmented structure maintains reasonable device complexity.
Solution Approach 2:
The patent applies different operational states to different parts of the system: selected string units have their selection transistors turned on with boosted word lines, while non-selected string units have their selection transistors turned off. This local differentiation reduces overall power consumption while maintaining functional complexity only where needed.
3Speed
If non-selected string units have their selection transistors turned on, then channel potentials are raised, but current consumption increases
Solution Approach 1:
The patent segments the memory device into multiple independent memory cell arrays with separate selection mechanisms. This allows the boosting action to be localized only to the selected array, raising channel potentials and word line boosting speed only where needed, while non-selected arrays consume minimal current with their selection transistors turned off.
Solution Approach 2:
The patent applies the boosted channel potential condition locally only to selected string units, while non-selected string units maintain lower potentials with their selection transistors off. This local quality differentiation achieves fast word line boosting in active regions without the penalty of high current consumption across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves processing capability and reduces power consumption by increasing word line boosting speed and minimizing current consumption during read and program operations.
Implementation Method 1
a capacitor coupling the first bit line to the second bit line
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes, a first string in which a first selection transistor, a first memory cell, and a second selection transistor are coupled in series, a second string in which a third selection transistor, a second memory cell, and a fourth selection transistor are coupled in series, a word line, a first selection gate line, a second selection gate line, a third selection gate line, a fourth selection gate line, a first bit line, and a second bit line. In a read operation of the first memory cell, when a voltage of the word line is raised to a first voltage, a second voltage is applied to the first bit line and a third voltage higher than the second voltage is applied to the second bit line.