Memory String Layout With Isolated Pillars to Prevent Over-Erasing
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Solution Overview
Problem
Non-volatile memory devices, such as flash memory, face issues with over erasing due to lower threshold voltage, leading to leakage current problems.
Innovation Solution
A semiconductor device design where the channel layer has a first location surrounded by the memory structure and a second location exposed, with the first conductive pillar and second conductive pillar electrically isolated and coupled to opposite locations, allowing for complete current shutdown to prevent over erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory structure surrounds both locations of the channel layer to improve memory functionality, then the memory structure provides complete coverage, but over erasing and leakage current occur due to lower threshold voltage
Solution Approach 1:
The patent divides the channel layer into two distinct locations: a first location surrounded by the memory structure and a second location exposed from the memory structure. This segmentation allows different regions of the channel layer to serve different functions - the first location for memory operations and the second location for preventing over-erasing and leakage current
Solution Approach 2:
The patent applies different structural configurations to different locations of the channel layer. The first location has the memory structure surrounding it for proper memory function, while the second location is exposed from the memory structure to prevent harmful effects. This local differentiation resolves the contradiction by providing tailored solutions to different regions
2Productivity
If the threshold voltage is reduced to improve memory performance, then the memory device operates more efficiently, but over erasing and leakage current problems arise
Solution Approach 1:
By segmenting the channel layer into two locations with different memory structure coverage, the patent enables the system to maintain low threshold voltage for efficient operation while preventing over-erasing through the exposed second location
Solution Approach 2:
The exposed second location of the channel layer provides a local region where electrons can be retained even when the threshold voltage is low, preventing over-erasing and leakage current while allowing the rest of the device to operate efficiently
Data Source
AI summary
A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first portion and a second portion of the channel layer. The first portion is opposite to the second portion. The first portion is surrounded by the memory structure, and the second portion is exposed from the memory structure.