Memory String Programming With Selective Channel Cleaning
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Solution Overview
Problem
Existing NAND Flash memory devices face challenges in reducing program time while mitigating the adverse effects of residual channel potential and hot carrier injection (HCI) during verify cycles, which prolong the duration of each cycle and affect read operations.
Innovation Solution
Implementing separated channel cleaning schemes that skip the pre-pulse and/or post-pulse stages for certain memory strings, particularly those already programmed, to reduce program time and minimize HCI effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-pulse and post-pulse stages are applied to all memory strings during verify cycles, then residual channel potential and HCI effects are mitigated, but program time is prolonged
Solution Approach 1:
The patent applies different verify cycle stages to different memory strings based on their programming status. Memory strings that have been successfully programmed skip the pre-pulse and post-pulse stages, while memory strings that require programming receive the full treatment. This local differentiation resolves the contradiction by applying channel cleaning only where necessary, reducing overall program time while maintaining reliability for strings that need it.
Solution Approach 2:
Instead of applying the full pre-pulse and post-pulse sequence to all memory strings, the patent applies partial action only to those memory strings that have not yet been successfully programmed. The controller determines which strings need cleaning based on verify results, and applies the cleaning stages selectively. This partial application reduces the total time spent on verify cycles while ensuring that strings requiring programming receive adequate channel cleaning.
2Object-affected harmful factors
If pre-pulse stage is applied to all memory strings, then HCI effects are reduced, but the duration of each verify cycle increases
Solution Approach 1:
The patent implements local quality by applying the pre-pulse stage selectively to only those memory strings that have not yet been successfully programmed. The controller identifies which strings require programming and applies the pre-pulse stage only to those strings, while skipping it for strings that have already been programmed. This approach reduces HCI effects where needed without unnecessarily extending the verify cycle duration for all strings.
Solution Approach 2:
The patent applies the skipping principle by allowing verify cycles to proceed without the pre-pulse stage for memory strings that have already been successfully programmed. The controller detects successful programming and skips the pre-pulse stage for those strings, rushing through the verify cycle more quickly. This reduces the overall verify cycle duration while still applying the pre-pulse stage to strings that need programming to mitigate HCI effects.
3Reliability
If channel cleaning stages are applied to all memory strings, then read operation reliability is improved, but overall programming efficiency decreases
Solution Approach 1:
The patent applies local quality by differentiating between memory strings based on their programming status. Successfully programmed strings skip the post-pulse stage, while strings requiring programming receive the full post-pulse treatment. This ensures read operation reliability is maintained for strings that need programming, while improving programming efficiency by avoiding unnecessary cleaning stages for strings that are already programmed correctly.
Solution Approach 2:
The patent applies partial action by providing the post-pulse stage only to memory strings that have not yet been successfully programmed, rather than applying it to all strings. The controller determines which strings need the post-pulse stage based on verify results and applies it selectively. This partial application maintains read reliability for strings requiring programming while improving overall programming efficiency by reducing redundant operations.
Data Source
AI summary
The present disclosure provides memory devices, memory systems, and methods for operating a memory device. In certain aspects, a disclosed memory device comprises memory strings each comprising a drain select gate (DSG) transistor, memory cells, and a source select gate (SSG) transistor, the method comprising: programming a first memory cell of a first memory string in a subset of memory strings, wherein the SSG transistors of the subset of memory strings are coupled with each other. In certain aspects, a disclosed method for operating the disclosed memory device comprises verifying the first memory cell without applying a pre-pulse stage to the first memory cell, programming a second memory cell of a second memory string in the subset after programming the first memory cell, and verifying the second memory cell including applying the pre-pulse stage to the second memory cell.