3D Memory Cell String Separation for Uniform Channel Voltage
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing data storage capacity and performance, particularly in efficiently arranging memory cells to increase storage density.
Innovation Solution
A semiconductor device with a gate stacking structure featuring alternately stacked interlayer insulation layers and gate electrodes, including a selection gate electrode, and channel structures that penetrate the gate stacking structure, with a separation pattern to stabilize the memory cell string.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three dimensions instead of two dimensions, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking gate electrodes and channel structures vertically, transitioning from two-dimensional planar arrangement to three-dimensional vertical stacking. This enables increased storage capacity by utilizing the vertical dimension while maintaining manageable device complexity through systematic structural design.
2Reliability
If a separation pattern is introduced to stabilize the memory cell string, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The separation pattern divides the gate electrode into multiple segments along the channel length direction, creating isolated regions that stabilize the memory cell string. This segmentation approach improves reliability by preventing electrical interference between adjacent cells while maintaining manufacturing feasibility through standard photolithography processes.
3Reliability
If channel structures are made continuous to ensure stable memory cell operation, then reliability is improved, but productivity decreases due to additional manufacturing steps
Solution Approach 1:
The gate dielectric layer and channel layer are formed continuously before the separation pattern is introduced. This preliminary formation of continuous structures ensures reliable memory cell operation, while the subsequent separation pattern formation uses standard etching and filling processes that do not significantly impact overall manufacturing productivity.
Data Source
AI summary
A semiconductor device including a gate stacking structure, a plurality of channel structures, and a separation pattern. The plurality of channel structures including an adjacent channel structure including a first portion having a surface adjacent to the separation pattern and a separation surface spaced apart from the separation pattern. At least one of the gate dielectric layer or the channel layer is on the separation surface and the adjacent surface in the first portion of the adjacent channel structure.