3D Memory String Source Line Segmentation for Reliability
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in achieving high operational reliability due to limitations in the design and fabrication of memory strings, particularly in the integration and electrical coupling of source lines and channel layers.
Innovation Solution
The semiconductor device incorporates a well plate with a separation layer and an auxiliary source line layer, along with a stack structure that includes channel layers passing through the stack, allowing for improved electrical coupling between the well plate and the source line layers, enhancing the reliability of memory strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional semiconductor device is constructed with stacked gate electrodes and channel layers, then high integration is achieved, but operational reliability deteriorates due to limitations in source line integration and electrical coupling
Solution Approach 1:
The source line system is segmented into multiple independent source line layers (first source line layer and second source line layer) that are electrically isolated from each other. Each source line layer can be independently controlled and connected to channel layers, allowing for improved reliability through redundancy and independent operation of each segment.
Solution Approach 2:
The source lines are extended from a single-plane configuration to a multi-layer three-dimensional structure. The first and second source line layers are positioned at different vertical levels, with channel layers passing through both layers, creating a spatially distributed electrical coupling system that improves reliability while maintaining high integration.
2Device complexity
If source lines are integrated in the conventional single-layer configuration, then device complexity is reduced, but electrical coupling efficiency deteriorates
Solution Approach 1:
The source line architecture transitions from a two-dimensional single-layer configuration to a three-dimensional multi-layer structure. The first and second source line layers are positioned at different vertical levels with channel layers extending through both, enabling efficient electrical coupling across multiple dimensions while maintaining manageable device complexity through systematic layering.
3Reliability
If channel layers are extended to pass through multiple source line layers, then electrical coupling is improved, but manufacturing precision requirements increase
Solution Approach 1:
The channel layers are formed to extend through the entire depth of the structure, passing through both the first and second source line layers before the source line layers are fully formed. This preliminary formation of channel layers establishes the alignment reference for subsequent source line layer deposition, reducing the precision requirements for later manufacturing steps.
Solution Approach 2:
The channel layers are nested within the multi-layer structure, passing through both source line layers and gate electrodes. This nested configuration allows the channel layers to serve as a central structural element that automatically defines the alignment pathway, reducing the need for high-precision alignment operations during subsequent manufacturing steps.
Data Source
AI summary
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a memory string including memory cells coupled to each other in series via a channel layer, the memory string coupled between a bit line and a second source line. The semiconductor device may include a first source line electrically coupled to the second source line through the channel layer.