Vertical Memory String Layout With Protective Stopper-Line Isolation
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in increasing integration density due to the high cost of miniaturization equipment and the need for advanced pattern-forming technologies, which restricts their performance and cost-effectiveness.
Innovation Solution
A semiconductor memory device design incorporating a mold structure with stacked wordlines, channel structures that penetrate vertically, block separation areas, protective structures, string separation structures, bitlines, and bitline contacts, which enhance integration density and process margins while maintaining product reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional semiconductor memory devices use miniaturization equipment to increase integration density, then integration density improves, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from conventional two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, with wordlines, bitlines, and channel structures arranged in three dimensions. This dimensional change allows integration density to increase without requiring further miniaturization of individual cell features, thereby avoiding the need for expensive advanced lithography equipment.
2Quantity of substance
If conventional two-dimensional semiconductor memory devices continue to scale down, then integration density increases, but process margins deteriorate
Solution Approach 1:
By stacking memory cell layers vertically, the patent achieves higher integration density while maintaining larger lateral feature sizes. The vertical stacking approach decouples the integration density from the lateral pattern dimensions, allowing process margins to be preserved even as overall device capacity increases through additional stacked layers.
3Quantity of substance
If three-dimensional semiconductor memory devices are implemented, then integration density improves, but device complexity increases
Solution Approach 1:
The three-dimensional memory device is divided into multiple identical or similar memory cell layers stacked vertically. Each layer contains wordlines, bitlines, and channel structures that follow consistent patterns. This segmentation into repeating units simplifies the manufacturing process, as the same fabrication steps can be applied repeatedly to each layer, reducing overall device complexity despite the three-dimensional architecture.
Solution Approach 2:
Multiple memory cell layers are nested vertically, with each layer containing complete functional elements (wordlines, bitlines, channels). The nested stacking allows compact three-dimensional integration while maintaining modular structure that simplifies design and fabrication compared to non-modular three-dimensional approaches.
Data Source
AI summary
A semiconductor memory device includes a mold structure including a plurality of wordlines on a front side of a first substrate, and a string selection line and a stopper line on the plurality of wordlines. A channel structure extends in a vertical direction to penetrate the mold structure. A block separation area extends in a first direction to cut the mold structure. A protective structure is interposed between the block separation area and the stopper line and not between the block separation area and the string selection line and not between the block separation area and the plurality of wordlines. A string separation structure extends in the first direction to cut the string selection line and the stopper line. A bitline extends in a second direction on the mold structure. A bitline contact connects the channel structure and the bitline.